PhD Dissertations

M.S. Theses

Journal Papers

• H. Zheng, H. Yao, T. Yoneda, Modular Model Checking of Large Asynchronous Designs with Efficient Abstraction Refinement,
  IEEE Transactions on Computers, Accepted, 2009.
• H. Yao, H. Zheng, Automated Interface Refinement for Compositional Verification (bibtex),
  in IEEE Transactions on COMPUTER-AIDED DESIGN and Integrated Circuits and Systems, 28(3), 2009.
• H. Zheng, J. Ahrens, T. Xia, A Compositional Method with Failure-Preserving Abstractions for Asynchronous Design Verification, (bibtex) ,
  in IEEE Transactions on COMPUTER-AIDED DESIGN of Integrated Circuits and Systems, 27(7), 2008.
• H. Zheng, C. Myers, D. Walter, S. Little, and T. Yoneda, Verification of Timed Circuits with Failure Directed Abstractions (bibtex) ,
  in IEEE Transactions on COMPUTER-AIDED DESIGN of Integrated Circuits and Systems, 25(3), 2006.
• H. Zheng, E. Mercer, and C. Myers, Modular Verification of Timed Circuits Using Automatic Abstraction (bibtex) ,
  IEEE Transactions on COMPUTER-AIDED DESIGN of Integrated Circuits and Systems, 22(9), September, 2003.

Conference Papers

• H. Zheng, H. Yao, T. Yoneda, Synchronization-Based Abstraction Refinement for Modular Verification of Asynchronous Designs
  IEEE Computer Society Annual Symposium on VLSI (ISVLSI), May, 2009.
• T. Xia, H. Zheng, and A Ginawi, Self-Refereed On-Chip Jitter Measurement Circuit Using Vernier Oscillators,
  IEEE Computer Society Annual Symposium on VLSI, May, 2005.
• T. Xia, P. Song, and H. Zheng, Characterizing the VCO jitters due to the Digital Simultaneous Switching Noise,
  ACM Great Lakes Symposium on VLSI, April, 2005.
• H. Zheng, C. Myers, D. Walter, S. Little, and T. Yoneda, Verification of timed circuits with failure directed abstractions,
  in IEEE International Conference on Computer Design, October, 2003
• E. Mercer, C. J. Myers, T. Yoneda, and H. Zheng, Modular synthesis of timed circuits using partial orders on LPNs,
  Theory and Practice of Timed Systems, TPTS '02, April, 2002.
• H. Zheng, E. Mercer, and C. Myers, Automatic abstraction for verification of timed circuits and systems,
  in Computer Aided Verification (CAV), pages 182-193, July, 2001.
• C. Myers, W. Belluomini, K.Killpack, E. Mercer, E. Peskin, and H. Zheng, Timed Circuits: A New Paradigm for High-Speed Design,
  2001 Asia and South Pacific Design Automation Conference, February, 2001 (invited paper).
• M. Bachman, H. Zheng, and C. Myers, Architectural Synthesis of Timed Asynchronous Systems,
  IEEE International Conference on Computer Design (ICCD), October, 1999.
• C. Myers and H. Zheng, An Asynchronous Implementations of the MAXLIST Algorithm,
  1997 International Conference on Acoustics, Speech, and Signal Processing, April, 1997.

Other Documents:

• Hao Zheng, An introduction of system verification and model checking, talk presentation.
• Ryan Mabry, Asynchronous Implementation of 8051 Microcontroller, Honor's Thesis, USF, 2005.
• Hao Zheng, A Compositional Method with Failure-Preserving Abstraction for Asynchronous Design Verification, technical report, 2007.