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Current Ph.D. Students |
Ph.D. Graduates
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M.S. Thesis Students
Vishwanath Sairaman, Low Power High Performance Embedded Systems, Ph.D.
Candidate
Narender Hanchate, Leakage Power Analysis and Optimization, Ph.D.
Candidate
Upavan Gupta, Framework for Resource Management in Multi-Crisis
Environments, Ph.D. Candidate.
Elizabeth Horton, VLSI Design Automation, Ph.D. Candidate
Mahalingam Venkataraman, VLSI Design Automation, Ph.D. Student
Ashwath Oruganti, VLSI Design Automation, Ph.D. Student
Michael Pham, VLSI Design Automation, Ph.D. Student
Soumyaroop Roy, Hardware Software Co-Design, Ph.D. Student, Jointly with
Dr. S. Katkoori, CSE
Kevin Rojas, Hardware and Software for SKIN Interface, IGERT Ph.D.
Fellow, Jointly with Dr. R. Sankar, E.E.
Saraju P. Mohanty, High Level Synthesis of Low Power High Performance Datapath Designs, graduated Dec 2003; Assistant Professor, Uni. of North
Texas, Denton.
Ashok Murugavel, Power Estimation and Optimization in CMOS VLSI Circuits,
August 2003, Senior CAD Engineer, Intel Corporation, Hillsborough,
Oregon.
- SIGMA XI Tampa Bay Chapter Outstanding Dissertation Award
- USF Graduate Council Outstanding Dissertation Award.
Sanjukta Bhanja, Power Estimation in CMOS Circuits Using Bayesian Networks,
July 2002, Assistant Professor, University of South Florida, Dept of EE.
R. Venkatramana, Partitioning and Scheduling for Heterogeneous Computing
Systems, May 2000, Senior Design Engineer, Honeywell Inc., Clearwater,
FL.
Abdel Ejnioui, Routing and Partitioning in FPGA-based Emulation Systems,
August 1999; Assistant Professor, School of EECS, Uni. of Central
Florida, 2001.
Hitoshi Oi, Bidirectional Ring Based Multiprocessor, Nov 1999, Senior
Architect, HaL Computer Systems, joining FAU as faculty in 2001.
R. Chandramouli, Theory and Application of Sequential Detection under
Dependence, Jan 1999; Assistant Prof., Dept. of ECE, Iowa State
University; Stevens Inst. of Technology, NJ;
- USF Graduate Council
Outstanding Dissertation Award.
Vijay Krishna, High Level Techniques for Power Estimation, Analysis and
Optimization, Jan 1999; Member of Technical Staff, Agilent Research
Labs, Palo Alto;
- USF Graduate Council Outstanding Dissertation Award.
N. Vijaykrishnan, ”Issues in the Design of a Java Processor”, July 1998;
Associate Professor, Dept. of CSE, Penn State University, Univeristy
Park, PA.
V. Ramaswamy, Lossless Image Compression Using Wavelet Decomposition,
April 1998; Member of Technical Staff, Bell Laboratories, Holmdel, NJ.
G. Chiruvolu, Efficient Transportation of VBR Video Traffic in ATM
Networks, April 1998; Research Scientist, Alcatel, Richardson, TX.
Minesh Patel, RAPID: A Real-Time System for Intelligent Decision Making, Aug
1997; Senior Systems Engineer, Satellite and Advanced Processing
Avionics, Honeywell Space Systems, Clearwater, FL.
Raghu Sastry, VLSI Architectures for Pattern Matching and Recognition, Aug
94; Senior Member of Technical Staff, Redswitch Inc., Campbell, CA;
- USF Graduate Council Outstanding Dissertation Award
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SIGMA CHI
Outstanding Dissertation Award.
K. Hughes, Multi-sensor Based Confidence Measurement Model for Robot
Path Planning, May 1994; Faculty, Dept. of ECE, Uni. of Pacific,
Stockton, CA.
K. V. Namuduri, Gabor Filter Based Models for Low-level Vision, Sept
1992; Associate Professor, Wichita State University, Kansas; previously
at CTSPS, Clark Atlanta University, Atlanta, GA.
Adam Francis, Optimization in VLSI Systems Using Non-linear
Optimization Techniques, Dec 2005 (Expected).
Venkataraman Mahalingam, MSCP Improving Accuracy in Logarithmic
Multiplication Using Operand Decomposition, May 2005.
Abhijeet Lothe, 3-D Virtual Reality Rendering of Human Body, July
2005.
Brian Hayes, Instruction Scheduling for Low Power, May 2005.
Vasanth K. Ramesh, Scheduling in Heterogenous Systems Using Game Theory, May
2005.
Neeta Singh, Compiler-Level Power Optimization, March 2005.
Rashmi Shetty, Nash Equilibrium Solution and Software Tool for
Dynamic Environments, Dec 2004.
Upavan Gupta, Multi-event Crisis Management in Urban Environment,
Dec 2004.
Prashant Dhongale, Power Optimization at Instruction Level, Dec
2003.
Karthik Balakrishnan, A VLSI System for Digital Watermarking in
Images, Dec 2003.
Ravi Namballa, CHESS: A High Level Synthesis Tool for CMOS Circuits, May
2003.
Narender Hanchate, A New Technique for Leakage Reduction in CMOS Circuits, May
2003.
O. Eizenchtadt, Parallel Clustering in a Heterogenous Computing Network,
November 2002.
Sunil Chappidi, Dynamic Scheduling for Heterogenous Computing Systems, Dec
2002.
K. Sitaraman, VLSI for Pattern Matching, Dec 2001.
H. Ramamurthy, RTL Level Power Estimation for Control Path Circuits,
August 2000.
P. Shenoy, Physical Design of FPGAs, Dec 1999.
S. Srinivasan, Synthesis for Low Power, Aug 2001.
A. Pannikar, ”A Partitioning Algorithm for Delay driven scheduling of
Field Programmable Gate Arrays”, July 1999 (Uni. of Texas at El Paso).
Ashok Murugavel, ”A Fast and Accurate Technique for Estimation of Average
Power in Digital CMOS VLSI Circuits”, July 1999 (Uni. of Texas at El
Paso).
V. Mistry, ”A VLSI Architecture for Data Encryption”, Jan 1999.
Wallon Henriques, ”A New Algorithm for Coloring Classic B/W Movies”,
April 1998.
S. Chavali, ”A Sequential Linear Power Estimator Algorithm for CMOS
Circuits”, Oct 1998.
S. Ragothaman, ”A VLSI Chip for Motion Estimation”, Jan 1999.
S. Kumar, ”Adaptive Quantization for Video Compression and
Transmission”, Dec 1997.
V. Sundaresan, ”A VLSI Chip for Discrete Cosine Transform Computation”,
Dec 1997.
R. Gadekarla, ”A New Profiling Tool for JAVA Execution”, Dec 1997.
S. Crasta, ”A New Algorithm for Lossless Compression of Text Databases”,
Dec 1997.
P. Singh, ”A new DCT Algorithm and its VLSI Architecture for MPEG-II
Audio Layer Standard”, May 1997.
R. Anand, ”A VLSI Chip for Buffer Allocation & Management in ATM
Networks”, May 1997.
R. Venkataramana, ”A VLSI Hardware Router for MIMD Systems”, Aug 1997.
R. Margapur, ”A VLSI System for Neural Network Implementation”.
A. Rasquinha, ”A Connected Component Labeling Chip & FPGA
Implementation”, Sept 1996.
N. Bhavanishankar, ”A VLSI Chip for Image Processing”, April 1996.
R. Chandra, ”A VLSI Chip for Maximal matching in Bipartite Graphs”,
February 1996.
R. Sathyamurthy, ”Intelligent Decision Making for Underwater
Navigation”, Apr 1996.
A. Konduru, ”A Compression Algorithm for Relational Databases”, Dec
1997.
V. Sundaram, ”3-D Volumetric Medical Data Compression”, September 1996.
Weyron Henriques, ”VLSI System for Enhancement of Digital Mammograms”,
Oct 1996.
S. Shivaraman,”Joint Source and Channel Coding”, August 1996.
H. Rashedi,”Lossless Compression of Digital Mammogram Images”,
December 1995.
P. Solarzano,”FPGA Implementation of LZWCompression for Modems”.
S. Aruru, ”VLSI Chip for Image Compression with Variable Block
Segmentation”, Dec 1995.
V. Krishna,”VLSI Chip for Tree Pattern Matching”, April 1996.
N. Saxena,”Implementation of Bayesian Networks on Hypercube”, Dec
1995.
R. Motamarri, ”VLSI Architecture for CBS Matching”, December 1995.
A. Ejnioui, ”Parallel Algorithms for Tree Pattern Matching”, March 1995.
B. D. Kiran, ”VLSI Architectures for Image Thinning”, April 1995.
V. Natarajan, ”VLSI Architectures for Data Compression,”April 1995
A. Karimpuzha, ”VLSI Architectures for Curve Generation,” July 1995.
S. Venugopal, ”A VLSI Architecture for Template Matching,” April 1994.
B. Parthasarathy, ”A VLSI Architecture for Robot Path Planning,” October
1993.
K. Remedios, ”A VLSI Chip for Approximate String Matching”, July 1993.
Shamira Kurji, ”A VLSI Chip for Motion Detection”.
Michael Sullivan, ”Systolic VLSI Designs for Data Compression”, May
1992.
Raghuveer Venkatesan, ”VLSI Architectures for Hierarchical Scene
Matching,” Aug 1992.
Jeffrey Fleider, ”A VLSI Chip for JPEG Baseline
Compression/Decompression”, May 1992.
Minesh Patel, ”Design of a 2-D VLSI Systolic Array Chip for Image
Processing”, May 1992.
Pat McCabe, ”A 2-D Systolic Array Architecture for Image and Signal
Processing”, May 1992.
R. Nyapathi, ”Hypotheses-based Object Recognition”, Dec 1991.
V.K. Sundaresan, ”Software and Hardware Solutions for Dynamic Time
Warping”, Dec 1991.
Balaji, K. R., ”A Systolic Chip for Computation of Join in Relational
Databases”, Dec 1991.
Elizabeth Meyer, ”A CMOS VLSI Chip for Huffman-based Decompression”,
April 1991.
Selwyn Henriques, ”SALCOM: Systolic Architecture for LZ Data
Compression”, Dec 1990.
Suresh Subramanian, ”VLSI Algorithms for Connected Components Labeling”,
April 1990.
Sanjay J. Nichani, ”SAP: Systolic Array Processor for Computations in
Vision”, April 1990. |