2006   |  2005   |  2004   |  2003

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2006

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  1. N. Hanchate and N. Ranganathan, ”A Linear Time Algorithm for Wire Sizing with Simultaneous Optimization of Interconnect Delay and Crosstalk Noise”, Proc. Intl. Conf. on VLSI Design, Jan 2006 (ranked 1 out of 360 submissions and nominated for BEST PAPER AWARD)

  2. A. Oruganti and N. Ranganathan, ”Leakage Power Reduction in Dual-Vdd and Dual-Vth Designs by Probabilistic Analysis of Vth Variation, Proc. Intl. Conf. on VLSI Design, Jan 2006.

  3. V. Sairaman, N. Ranganathan, N. Singh, ”An Automatic Code Generation Tool for Partitioned Software in Distributed Systems”, Proc. Intl. Conf. on VLSI Design, Jan 2006.

  4. V. Mahalingam and N. Ranganathan, ”An Efficient and Accurate Logarithmic Multiplier Based on Operand Decomposition”, Proc. Intl. Conf. on VLSI Design, Jan 2006.

  5. U. Gupta and N. Ranganathan, ”FIRM: A Game Theory Based Multi-Crisis Management System  for Urban Environments”, To appear in Proc. of the Intl. Conf. on Sharing Solutions for Emergencies and Hazardous Environments, 2006.
2005

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  1. A Virtual Human Cadaver Navigation System, D. Hilbelink, N. Ranganathan and A. Loathe, U.S. Patent Application filed, July 2005.

  2. S. P. Mohanty and N. Ranganathan, Simultaneous Peak and Average Power Minimization during Datapath Scheduling, to appear in IEEE Trans. on Circuits and Systems Part I (TCAS-I), 2005.

  3. S. P. Mohanty, N. Ranganathan, and R. K. Namballa, A VLSI Architecture for Visible Watermarking in a Secure Still Digital Camera (S2DC) Design, to appear in IEEE Trans. on VLSI Systems (TVLSI), July 2005.

  4. S. P. Mohanty, N. Ranganathan, and S. K. Chappidi, ILP Models for Simultaneous Energy and Transient Power Minimization during Behavioral Synthesis, to appear in ACM Transactions on Design Automation of Electronic Systems (TODAES), 2005.

  5. S. P. Mohanty and N. Ranganathan, Energy Efficient Datapath Scheduling using Multiple Voltages and Dynamic Clocking, ACM Transactions on Design Automation of Electronic Systems (TODAES),Vol. 10, No. 2, April 2005, pp. 330-353.

  6. S. P. Mohanty, N. Ranganathan, and K. Balakrishnan, A Dual Voltage Dual Frequency Low Power VLSI Chip for Image Watermarking, Under revision in IEEE Trans. on Circuits and Systems Part I (TCAS-I), 2005.

  7. V. Mahalingam and N. Ranganathan, A Nonlinear Programming Based Power Optimization Methodology for Gate Sizing and Voltage Selection, IEEE computer society annual Symposium on VLSI, ISVLSI, May 2005.

  8. S. P. Mohanty, N. Ranganathan, and K. Balakrishnan, Design of a Low Power Image  Watermarking Encoder using Dual Voltage and Frequency, in Proceedings of the 18th IEEE International Conference on VLSI Design (VLSID), pp. 153-158, 2005.

  9. S. Bhanja, K. Lingasubramanian and N. Ranganathan, ”Estimation of Switching Activity in Sequential Circuits Using Dynamic Bayesian Networks, 18th International Conference in VLSI Design, pp.586-591, 2005
2004

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  1. S. P. Mohanty and N. Ranganathan, A Framework for Energy and Transient Power Reduction during Behavioral Synthesis, IEEE Transactions on VLSI Systems (TVLSI), Vol. 12, No. 6, June 2004, pp. 562-572.

  2. S. Bhanja and N. Ranganathan, ”Cascaded Bayesian Inferencing for Switching Activity Estimation”, IEEE Transactions on VLSI Systems, Dec 2004.

  3. R. Chandramouli, K.P. Subbalakshmi, and N. Ranganathan, “Channel-adaptive stochastic rate control for low bit rate wireless video transmission,” Special issue on Video Objects:  representation, creation, coding, transmission, manipulation and retrieval, Pattern Recognition Letters, 2004.

  4. N. Hanchate and N. Ranganathan, ”LECTOR: A Novel Technique for Leakage Reduction in CMOS VLSI Circuits”, IEEE Transactions on VLSI Systems, February 2004.

  5. S. Bhanja and N. Ranganathan, ”Comprehensive Modeling of Spatial and Temporal Correlation  Using Bayesian Networks for Switching Activity Estimation”, IEEE Transactions on VLSI Systems, 2004.

  6. R. Namballa, N. Ranganathan and A. Ejnioui, ”Control and Data Flow Graph Extraction for High Level Synthesis”, Proc. of IEEECS Annual Symposium on VLSI, Lafayette, Feb 19-20, 2004.

  7. A. K. Murugavel and N. Ranganathan, ”Gate Sizing and Buffer Insertion using Economic Models for Power Optimization”, to appear in Proc. Intl. Conf. on VLSI Design, Jan 2004 (BEST PAPER AWARD winner).

  8. N. Hanchate and N. Ranganathan, ”A New Technique for Leakage Reduction in Digital CMOS Circuits”, Proc. Intl. Conf. on VLSI Design, Jan 2004.

  9. A. K. Murugavel and N. Ranganathan, ”Game Theoretic Modeling of Voltage and Frequency  Scaling During Behavioral Synthesis,” Proc. Intl. Conf. on VLSI Design, Jan 2004.

  10. S. P. Mohanty, N. Ranganathan and R. K. Namballa, ” VLSI Implementation of Visible Watermarking for a Secure Digital Still Camera Design ”, Proceedings of the 17th IEEE International Conference on VLSI Design , pp.1063-1068, 2004.

  11. S. P. Mohanty, N. Ranganathan and S. K. Chappidi, ” ILP Models for Energy and Transient Power Minimization During Behavioral Synthesis ”, Proceedings of the 17th IEEE International Conference on VLSI Design , pp.745-748, 2004.

2003

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  1. A New Method for Leakage Reduction in CMOS VLSI Circuits, U.S. Patent Application filed, Dec 2003.

  2. A. Murugavel and N. Ranganathan, ”A Game-Theoretic Approach for Power Optimization during Behavioral Synthesis”, IEEE Transactions on VLSI Systems, 11(6), Pages 1031-1043, Dec 2003. A. Murugavel and N. Ranganathan, ”A Real Delay Switching Activity Simulator Based on Petri Net Modeling”, IEEE Transactions on VLSI Systems, 11(5), Pages 921-927, October 2003.

  3. S. Bhanja and N. Ranganathan, ”Switching Activity Estimation of VLSI Circuits Using Bayesian Networks”, 11(4), Pp. 558-567, August 2003.

  4. A. Ejnioui and N. Ranganathan, ”Routing on Field Programmable Switch Matrices”, IEEE  Transactions on VLSI Systems, 11(2), Pp. 283-287, April 2003.

  5. A. Ejnioui and N. Ranganathan, ”Multi-terminal net routing for partial crossbar-based multi-FPGA systems”, IEEE Transactions on VLSI Systems, 11(1), Pp. 71-78, Feb 2003.

  6. S.Bhanja and N. Ranganathan, Hardware Implementation of Data Compression, in Lossless Compression Handbook, edited by K. Sayood, , ISBN # 0-12-620861-1 Academic Press, 2003.

  7. N. Ranganathan and A. K. Murugavel, ”A microeconomic model for simultaneous gate sizing and voltage scaling for power optimization”, Intl. Conf. on Computer Design, 2003.

  8. N. Ranganathan and A. K. Murugavel, ”A Low Power Scheduler using Game Theory”, Intl.   Symp. On System Synthesis, 2003.

  9. S. P. Mohanty, N. Ranganathan and S. K. Chappidi, ” Power Fluctuation Minimization During Behavioral Synthesis using ILP-Based Datapath Scheduling”, Proceedings of the 21st IEEE International Conference on Computer Design , pp. 441-443, 2003.

  10. S. P. Mohanty, N. Ranganathan and S. K. Chappidi, ” Transient Power Minimization Through  Datapath Scheduling in Multiple Supply Voltage Environment”, Proceedings of the 10th IEEE International Conference on Electronics, Circuits and Systems, pp. 300-303, 2003

  11. S. P.Mohanty, N. Ranganathan and R. K. Namballa, ” VLSI Implementation of Invisible Digital Watermarking Algorithms Towards the Development of a Secure JPEG Encoder”, Proceedings of the IEEE Workshop on Signal Processing Systems, pp. 183-188, 2003.

  12. S. P.Mohanty, N. Ranganathan and S. Chappidi, ” Simultaneous Peak and Average  Power Minimization during Datapath Scheduling for DSP Processors, Proc. of ACM Great Lakes Symposium on VLSI (GLSVLSI 2003), pp. 215-220, Apr 28-29, 2003.

  13. S. P. Mohanty, N. Ranganathan and S. Chappidi, ” An ILP-Based Scheduling Scheme for Energy Efficient High Performance Datapath Synthesis ”, Proc. of IEEE International Symposium on Circuits and Systems (ISCAS 2003), pp. 313-316, May 25-28, 2003.

  14. S. P. Mohanty and N. Ranganathan, ”Energy Efficient Scheduling for Datapath Synthesis”, Proceedings of the 16th International Conference on VLSI Design 2003, pp.446-451, 2003.

  15. S. P. Mohanty and N. Ranganathan, ”A Framework for Energy and Transient Power Reduction during Behavioral Synthesis”, Proceedings of the 16th International Conference on VLSI Design 2003, pp.539- 545, 2003 (nominated for Best Paper Award ranked within top 5 of 220  submissions).

  16. A. Murugavel and N. Ranganathan, ”A Game-Theoretic Approach for Binding in Behavioral Synthesis”, Proc. Intl. Conf. on VLSI Design, Jan 2003, pp. 452-458.

  17. S. P. Mohanty, N. Ranganathan and S. K. Chappidi, ” Peak Power Minimization Through Datapath Scheduling”, Proceedings of the IEEE CS Annual Symposium on VLSI, pp.121-126, 2003