Books  |  Patents  |  Journals  |  Book Chapters  |  Refereed Conferences  |  VLSI Chips Designed/Supervised  |  Invited Talks

BOOKS

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  1. VLSI for Pattern Recognition and Artificial Intelligence, edited by N. Ranganathan, World Scientific Publishing Co., April 1995.
  2. VLSI Algorithms and Architectures: Fundamentals, edited by N. Ranganathan, IEEE Computer Society Press, June 1993.
  3. VLSI Algorithms and Architectures: Advanced Concepts, edited by N. Ranganathan, IEEE Computer Society Press, June 1993.

PATENTS

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  1. A Virtual Human Cadaver Navigation System, D. Hilbelink, N. Ranganathan and A. Loathe, U.S. Patent Application filed, July 2005.
  2. A New Method for Leakage Reduction in CMOS VLSI Circuits, U.S. Patent Application filed, Dec 2003.
  3. High Speed VLSI Hardware for Lempel-Ziv Based Data Compression, U.S. Patent 5,179,378, Dec 1993.
  4. Structure and Method for Dynamic Scene Analysis, U.S. Patent 5,604,821 Jan 1996.
  5. VLSI Architectures for Polygon Recognition, U.S. Patent 5,535,292, July 1996.
  6. VLSI Circuit Structure for Determining the Edit Distance Between Strings, U.S. Patent 5,553,272, Sept 1996.
  7. A VLSI Circuit Structure for Implementing JPEG Image Compression Standard, U.S. Patent 5,659,362, Aug 1997 and International Patent allowed recently.

JOURNAL PUBLICATIONS

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  1. S. P. Mohanty and N. Ranganathan, Simultaneous Peak and Average Power Minimization during Datapath Scheduling, to appear in IEEE Trans. on Circuits and Systems Part I (TCAS-I), 2005.
  2. S. P. Mohanty, N. Ranganathan, and R. K. Namballa, A VLSI Architecture for Visible Watermarking in a Secure Still Digital Camera (S2DC) Design, to appear in IEEE Trans. on VLSI Systems (TVLSI), July 2005.
  3. S. P. Mohanty, N. Ranganathan, and S. K. Chappidi, ILP Models for Simultaneous Energy and Transient Power Minimization during Behavioral Synthesis, to appear in ACM Transactions on Design Automation of Electronic Systems (TODAES), 2005.
  4. S. P. Mohanty and N. Ranganathan, Energy Efficient Datapath Scheduling using Multiple Voltages and Dynamic Clocking, ACM Transactions on Design Automation of Electronic Systems (TODAES),Vol. 10, No. 2, April 2005, pp. 330-353.
  5. S. P. Mohanty and N. Ranganathan, A Framework for Energy and Transient Power Reduction during Behavioral Synthesis, IEEE Transactions on VLSI Systems (TVLSI), Vol. 12, No. 6, June 2004, pp.562-572.
  6. S. P. Mohanty, N. Ranganathan, and K. Balakrishnan, A Dual Voltage Dual Frequency Low Power VLSI Chip for Image Watermarking, Under revision in IEEE Trans. on Circuits and Systems Part I (TCAS-I), 2005.
  7. S. Bhanja and N. Ranganathan,”Cascaded Bayesian Inferencing for Switching Activity Estimation”, IEEE Transactions on VLSI Systems, Dec 2004.
  8. A. Murugavel and N. Ranganathan, ”A Game-Theoretic Approach for Power Optimization during Behavioral Synthesis”, IEEE Transactions on VLSI Systems, 11(6), Pages 1031-1043, Dec 2003.
  9. A. Murugavel and N. Ranganathan, ”A Real Delay Switching Activity Simulator Based on Petri Net Modeling”, IEEE Transactions on VLSI Systems, 11(5), Pages 921-927, October 2003.
  10. S. Bhanja and N. Ranganathan, ”Switching Activity Estimation of VLSI Circuits Using Bayesian Networks”, 11(4), Pp. 558-567, August 2003.
  11. A. Ejnioui and N. Ranganathan, ”Routing on Field Programmable SwitchMatrices”, IEEE Transactions on VLSI Systems, 11(2), Pp. 283-287, April 2003.
  12. A. Ejnioui and N. Ranganathan,”Multi-terminal net routing for partial crossbar-based multi-FPGA systems”, IEEE Transactions on VLSI Systems, 11(1), Pp. 71-78, Feb 2003.
  13. R. Chandramouli, K.P. Subbalakshmi, and N. Ranganathan, “Channel-adaptive stochastic rate control for low bit rate wireless video transmission,” Special issue on Video Objects: representation, creation, coding, transmission, manipulation and retrieval, Pattern Recognition Letters, 2004.
  14. N. Hanchate and N. Ranganathan, ”LECTOR: A Novel Technique for Leakage Reduction in CMOS VLSI Circuits”, IEEE Transactions on VLSI Systems, February 2004.
  15. S. Bhanja and N. Ranganathan, ”Comprehensive Modeling of Spatial and Temporal Correlation Using Bayesian Networks for Switching Activity Estimation”, IEEE Transactions on VLSI Systems, 2004.
  16. A. Murugavel, N. Ranganathan, R. Chandramouli and S. Chavali, ”Least Square Estimation of Average Power in Digital CMOS Circuits”, IEEE Transactions on VLSI Systems, Vol. 10, No. 1, pp. 55-58, Feb 2002.
  17. M. Patel and N. Ranganathan, ”IDUTC: An Intelligent Decision Making System for Urban Traffic Control Applications”, IEEE Transactions on Vehicular Technology, 50(3), Pp. 816-829, May 2001.
  18. N. Ranganathan, M. Patel and R. Sathyamurthy, ”An Intelligent System for Failure Detection and Control in Autonomous Underwater Vehicle,” IEEE Transactions on SMC, i31(6), Pp. 762-767, Nov 2001.
  19. A. Ejnioui and N. Ranganathan, ”A partitioning algorithm for technology-mapped designs on single chip emulation systems”, IEEE Transactions on VLSI Systems, Vol. 9, No. 2, April 2001, Pp. 407-410.
  20. V.N. Ramaswamy, K. V. Namuduri and N. Ranganathan, ”Context-based Lossless Image Coding using EZW Framework”, IEEE Transactions on Circuits and Systems for Video Technology (CSVT), April 2001.
  21. N. Vijaykrishnan and N. Ranganathan, ”Object addressing support for a Java processor”, IEE Proceedings: Computers and Digital Techniques, Nov 2000, Vol. 147, No. 6, pp. 435-443.
  22. G. Chiruvolu, R. Sankar and N. Ranganathan, ”VBR Video Traffic Management Using a Predictor-Based Architecture”, ACM Computer Communications Journal, 2000, Vol. 23, No. 1, Pp. 62-70.
  23. Hitoshi Oi and N. Ranganathan, ”A Comparative Study of Bidirectional Ring and Crossbar Interconnection Networks”, Intl. Journal of Computers & Electrical Engineering, March 2001.
  24. Hitoshi Oi and N. Ranganathan, ”Utilization of Cache Area in On-Chip Multiprocessor”, Microprocessors and Microsystems, Jan 2001.
  25. Chandramouli and N. Ranganathan, ”Computing the Bivariate Gaussian Probability Integral”, IEEE Signal Processing Letters, 1999.
  26. R. Chandramouli, N. Vijaykrishnan and N. Ranganathan, ”Sequential Tests for Integrated Circuit Failures”, IEEE Transactions on Reliability, Dec 1998.
  27. R. Chandramouli and N. Ranganathan, A Generalized Sequential Sign Detector for Binary Hypothesis Testing, IEEE Signal Processing Letters, Vol. 5, No. 11, Pp. 295-298, Nov 1998.
  28. V.N. Ramaswamy, K.R. Namuduri and N. Ranganathan, ”Performance Analysis ofWavelets in Embedded Zerotree-based Image Coding Schemes”, IEEE Transactions on Signal Processing, Vol. 47, No. 3, Pp. 884-889, March 1999.
  29. V. Krishna, R. Chandramouli and N. Ranganathan, ”Computation of Lower Bounds for Switching Activity in CMOS Circuits Using Decision Theory”, IEEE Transactions on VLSI Systems, Pp. 125-129, March 1999.
  30. V. Krishna, N. Ranganathan and A. Ejnioui.”A Tree Matching Chip,” IEEE Transactions on VLSI Systems, June 1999.
  31. N. Ranganathan, N. Vijaykrishnan and N. Bhavanishankar, ”A Linear Array processor with Dynamic Frequency Clocking for Image Processing aPPLications”, IEEE Transactions on Circuits and Systems for Video Technology, Vol. 8, No. 4, August 1998, Pp. 435-445.
  32. R. Sastry and N. Ranganathan, ”A VLSI Architecture for Approximate Tree Matching”, IEEE Transactions on Computers, July 1997.
  33. G. Chiruvolu, R. Sankar and N. Ranganathan, ”Adaptive VBR Video Traffic Management for Higher Utilization of ATM Networks”, ACM SIGCOMM Computer Communication Review, Vol. 28, No. 3, July 1998, Pp. 31-46.
  34. R. Chandramouli, N. Ranganathan and S. Ramadoss, ”Adaptive Quantization and Fast Error Resilient Entropy Coding for Image Transmission”, IEEE Trans. on Circuits and Systems for Video Technology, Vol. 8, No. 4, August 1998, Pp. 411-421.
  35. N. Ranganathan, R. Sastry and R. Venkatesan, ”SMAC: A VLSI Architecture for Scene Matching”, Journal of Real-Time Imaging, Special Issue on VLSI for Image processing, Volume 4, No. 3, Pp. 171-180, June 1998.
  36. M. Kovac, M. Zagar and N. Ranganathan, ”Design and Optimization of a VLSI Architecture for Discrete Cosine Transform Used in Image Compression”, Journal of Computing and Information Technology, 3(4), Sept. 1996, Pp. 159-170.
  37. M. Kovac and N. Ranganathan, ”ACE: A VLSI Chip for Galois Field Based Exponentiation”, IEEE Trans. on Circuits and Systems, 43(4), Apr 1996, Pp. 289-297.
  38. M. Kovac and N. Ranganathan, ”JAGUAR: A VLSI Architecture for JPEG Image Compression Standard,” Proceedings of IEEE, Special Issue on Image and Video Compression, 83(2), Feb 1995; The paper won the Best Paper Award in International Conference on VLSI Design, January 1995.
  39. R. Sastry, N. Ranganathan and K. Remedios, ”CASM: A VLSI Chip for Approximate StringMatching,” IEEE Transactions on PAMI , 17(8), Aug1995, Pp. 824-830.
  40. N. Ranganathan, S. Subramaniam and R. Mehrotra, ”A Systolic Architecture for Finding Connected Components in an Image,” IEEE Trans. on Systems, Man and Cybernetics, 25(2), Feb1995, Pp. 415-423.
  41. N. Ranganathan, S. Roumaniak and K.R. Namuduri, ”A Lossless Image Compression Algorithm Using Variable Block Size Segmentation”, IEEE Transactions on Image Processing, 4 (10), Oct 1995, Pp.1396-1406.
  42. R. Sastry, N. Ranganathan and R.C. Jain, ”VLSI Architectures for High Speed Range Estimation”, IEEE Transactions on PAMI, 17(9), Oct 1995, Pp. 894-898.
  43. R. Sastry and N. Ranganathan, ”PMAC: A Polygon Matching Chip”, International Journal of Pattern Recognition and Artificial Intelligence, 9(2), April 1995.
  44. K. R. Namuduri, R. Mehrotra and N. Ranganathan, ”Efficient Computation of Gabor Filter Responses at Multiple Resolutions,” Pattern Recognition Journal, Vol. 27, October 1994.
  45. N. Ranganathan and R. Sastry, ”VLSI Architectures for Pattern Matching,” International Journal of Pattern Recognition and Artificial Intelligence, 8(4), 1994.
  46. S. Kumar, N. Ranganathan and D. Goldgof, ”Parallel Algorithms for Circle Detection in Images”, Pattern Recognition, 27(10), 1994.
  47. K. Hughes and N. Ranganathan, ”Modeling Sensor Confidence for Sensor Integration Tasks”, International Journal of Pattern Recognition and Artificial Intelligence, 8(6), 1994.
  48. K. R. Namuduri, N. Ranganathan and R. Mehrotra, ”Efficient Computation of Gabor Filter Responses at Multiple Resolutions,” Pattern Recognition, Vol. 27, October 1994.
  49. R. Sastry, N. Ranganathan and H. Bunke, ”VLSI Architectures for Polygon Recognition,” IEEE Transactions on VLSI Systems, 1(4), Dec 1993.
  50. A.Mukherjee, N. Ranganathan, J. Flieder and T. Acharya,”MARVLE: A VLSI Chip for Data Compression Using Tree-based Codes,” IEEE Trans. on VLSI Systems, 1(2), June 1993, pp. 203-214.
  51. M. Kovac, N. Ranganathan and M. Varanasi, ”SIGMA: A VLSI Systolic Array Implementation of a Galois Field Based Multiplication and Division Algorithm,” IEEE Trans. on VLSI Systems, 1(1), 1993, pp. 22-30.
  52. N. Ranganathan and S. Henriques, ”High Speed VLSI Designs for Lempel-Ziv based Data Compression”, IEEE Trans. on Circuits and Systems, CAS -II, Feb 1993, pp. 96-106.
  53. K. R. Namuduri, R. Mehrotra and N. Ranganathan,, ”Edge Detection Models based on Gabor Filters,” Pattern Recognition, Dec 1992.
  54. N. Ranganathan, K.R. Balaji and H.N. Srinidhi, ”A Systolic VLSI Chip for Relational Databases,” Microprocessors and Microsystems, Oct. 1992.
  55. A. Mukherjee, N. Ranganathan and M. Bassiouni, ”Efficient VLSI Designs for Data Transformation of Tree-based Codes,” IEEE Transactions on Circuits and Systems, 38(3), Mar 1991, pp. 306-314.
  56. N. Ranganathan, S. Nichani and R. Mehrotra, ”A VLSI Architecture for a Half-Edge Based Corner Detector,” Machine Vision and Applications, Vol. 4, 1991, pp. 165-181.
  57. N. Ranganathan, A. Mukherjee and M. A. Bassiouni, ”VLSI Algorithms for Data Compression,” Journal of Computer Systems Science and Engineering, Vol. 6, No. 4, October 1991, pp. 238-253.
  58. N. Ranganathan and R. Mehrotra, ”A VLSI Architecture for Dynamic Scene Analysis,” Computer Vision, Graphics and Image Processing : Image Understanding, Vol. 53, No. 2, March 1991, pp.189-197.
  59. S. Nichani, R. Mehrotra and N. Ranganathan, ”Corner Detection,” Pattern Recognition, Vol. 23, No. 11, Sept. 1990.
  60. M. Bassiouni, N. Ranganathan and A.Mukherjee, ”Enhancing Arithmetic and Tree-based Coding,”Information Processing and Management, Vol. 25, No. 3, Aug 1989, pp. 293-305.
  61. N. Ranganathan and M. Shah, ”A VLSI Architecture for computing Scale Space,” Computer Vision, Graphics and Image Processing, 43, pp. 178-204, August 1988.
  62. M. Bassiouni, N. Ranganathan and A.Mukherjee, ”Software and Hardware Enhancement of Arithmetic Coding,” Lecture Notes in Computer Science, Vol. 339, Springer-Verlag, 1988, pp. 120-132.
 
BOOK CHAPTERS

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  1. N. Ranganathan and S. Bhanja, ”Hardware Implementations”, invited chapter, in ”Data Compression” edited by K. Sayood, Academic Press, 2003.
  2. M. Patel and N. Ranganathan, ”A VLSI System for Intelligent Decision Making”, invited chapter in ”Neural Networks and Systolic Arrays”, edited by D. Zhang and S.K. Pal, World Scientific Publishers, 2002.
  3. N. Ranganathan and R. Venkataramana, ”Integrated Circuits”, invited article in 24-Volume Encyclopedia of Electrical Engineering, published by John Wiley and Sons, 1998.
  4. N. Ranganathan and S. Henriques, ”High Speed VLSI Designs for Lempel-Ziv based Data Compression”, IEEETCAS-II paper included in ”High Performance VLSI Signal Processing - Innovative Architectures and Algorithms Vol I & II” edited by K.J. Ray Liu and K. Yao, IEEE Press, 1997

REFEREED CONFERENCE PAPERS

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  1. N. Hanchate and N. Ranganathan, ”A Linear Time Algorithm for Wire Sizing with Simultaneous Optimization of Interconnect Delay and Crosstalk Noise”, Proc. Intl. Conf. on VLSI Design, Jan 2006 (ranked 1 out of 360 submissions and nominated for BEST PAPER AWARD).
  2. A. Oruganti and N. Ranganathan, ”Leakage Power Reduction in Dual-Vdd and Dual-Vth Designs by Probabilistic Analysis of Vth Variation, Proc. Intl. Conf. on VLSI Design, Jan 2006.
  3. V. Sairaman, N. Ranganathan, N. Singh, ”An Automatic Code Generation Tool for Partitioned Software in Distributed Systems”, Proc. Intl. Conf. on VLSI Design, Jan 2006.
  4. V. Mahalingam and N. Ranganathan, ”An Efficient and Accurate Logarithmic Multiplier Based on Operand Decomposition”, Proc. Intl. Conf. on VLSI Design, Jan 2006.
  5. U. Gupta and N. Ranganathan, ”FIRM: A Game Theory Based Multi-Crisis Management System for Urban Environments”, To appear in Proc. of the Intl. Conf. on Sharing Solutions for Emergencies and Hazardous Environments, 2006.
  6. V. Mahalingam and N. Ranganathan, A Nonlinear Programming Based Power Optimization Methodology for Gate Sizing and Voltage Selection, IEEE computer society annual Symposium on VLSI, ISVLSI, May 2005.
  7. S. P. Mohanty, N. Ranganathan, and K. Balakrishnan, Design of a Low Power Image Watermarking Encoder using Dual Voltage and Frequency, in Proceedings of the 18th IEEE International Conference on VLSI Design (VLSID), pp. 153-158, 2005.
  8. S. Bhanja, K. Lingasubramanian and N. Ranganathan, ”Estimation of Switching Activity in Sequential Circuits Using Dynamic Bayesian Networks, 18th International Conference in VLSI Design, pp.586-591, 2005.
  9. R. Namballa, N. Ranganathan and A. Ejnioui, ”Control and Data Flow Graph Extraction for High Level Synthesis”, Proc. of IEEECS Annual Symposium on VLSI, Lafayette, Feb 19-20, 2004.
  10. A. K. Murugavel and N. Ranganathan, ”Gate Sizing and Buffer Insertion using Economic Models for Power Optimization”, to appear in Proc. Intl. Conf. on VLSI Design, Jan 2004 (BEST PAPER AWARD winner).
  11. N. Hanchate and N. Ranganathan, ”A New Technique for Leakage Reduction in Digital CMOS Circuits”, Proc. Intl. Conf. on VLSI Design, Jan 2004.
  12. A. K. Murugavel and N. Ranganathan, ”Game Theoretic Modeling of Voltage and Frequency Scaling During Behavioral Synthesis,” Proc. Intl. Conf. on VLSI Design, Jan 2004.
  13. S. P. Mohanty, N. Ranganathan and R. K. Namballa, ” VLSI Implementation of Visible Watermarking for a Secure Digital Still Camera Design ”, Proceedings of the 17th IEEE International Conference on VLSI Design , pp.1063-1068, 2004.
  14. S. P. Mohanty, N. Ranganathan and S. K. Chappidi, ” ILP Models for Energy and Transient Power Minimization During Behavioral Synthesis ”, Proceedings of the 17th IEEE International Conference on VLSI Design , pp.745-748, 2004.
  15. N. Ranganathan and A. K. Murugavel, ”A microeconomic model for simultaneous gate sizing and voltage scaling for power optimization”, Intl. Conf. on Computer Design, 2003.
  16. N. Ranganathan and A. K. Murugavel, ”A Low Power Scheduler using Game Theory”, Intl. Symp. on System Synthesis, 2003.
  17. S. P. Mohanty, N. Ranganathan and S. K. Chappidi, ” Power Fluctuation Minimization During Behavioral Synthesis using ILP-Based Datapath Scheduling”, Proceedings of the 21st IEEE International Conference on Computer Design , pp. 441-443, 2003.
  18. S. P. Mohanty, N. Ranganathan and S. K. Chappidi, ” Transient Power Minimization Through Datapath Scheduling in Multiple Supply Voltage Environment”, Proceedings of the 10th IEEE International Conference on Electronics, Circuits and Systems, pp. 300-303, 2003.
  19. S. P.Mohanty, N. Ranganathan and R. K. Namballa, ” VLSI Implementation of Invisible Digital Watermarking Algorithms Towards the Development of a Secure JPEG Encoder”, Proceedings of the IEEE Workshop on Signal Processing Systems, pp. 183-188, 2003.
  20. S. P.Mohanty, N. Ranganathan and S. Chappidi, ” Simultaneous Peak and Average PowerMinimization during Datapath Scheduling for DSP Processors, Proc. of ACM Great Lakes Symposium on VLSI (GLSVLSI 2003), pp. 215-220, Apr 28-29, 2003.
  21. S. P. Mohanty, N. Ranganathan and S. Chappidi, ” An ILP-Based Scheduling Scheme for Energy Efficient High Performance Datapath Synthesis ”, Proc. of IEEE International Symposium on Circuits and Systems (ISCAS 2003), pp. 313-316, May 25-28, 2003.
  22. S. P. Mohanty and N. Ranganathan, ”Energy Efficient Scheduling for Datapath Synthesis”, Proceedings of the 16th International Conference on VLSI Design 2003, pp.446-451, 2003.
  23. S. P. Mohanty and N. Ranganathan, ”A Framework for Energy and Transient Power Reduction during Behavioral Synthesis”, Proceedings of the 16th International Conference on VLSI Design 2003, pp.539-545, 2003 (nominated for Best Paper Award ranked within top 5 of 220 submissions).
  24. A. Murugavel and N. Ranganathan, ”A Game-Theoretic Approach for Binding in Behavioral Synthesis”, Proc. Intl. Conf. on VLSI Design, Jan 2003, pp. 452-458.
  25. S. P. Mohanty, N. Ranganathan and S. K. Chappidi, ” Peak Power Minimization Through Datapath Scheduling”, Proceedings of the IEEE CS Annual Symposium on VLSI, pp.121-126, 2003.
  26. S. Bhanja and N. Ranganathan,”Modeling Switching Activity Using Cascaded Bayesian Networks for Correlated Input Streams”, International Conference on Computer Design, pp. 388-390, 2002.
  27. A. Murugavel and N. Ranganathan, ”Power estimation of sequential circuits using hierarchical colored hardware petri net modeling”, Proc. IEEE/ACM Intl. Symp. on Low Power Electronic Design, 267-270, Aug 2002.
  28. K.Sitaraman, N.Ranganathan and A. Ejnioui, ”A VLSI Architecture for Object Recognition Using Tree Matching,” Proc. 13th IEEE Conference on Application-Specific Systesa Architectures and Processors (ASAP) 2002, pp 325-334.
  29. A.Murugavel and N. Ranganathan, ”Average Power Estimation in CMOS Circuits Using Petrinet Modeling”, Proc. IEEE/ACM Design Automation Conference, 455-460, June 2002.
  30. S. Mohanty, N. Ranganathan, V. Krishna, ”Datapath Scheduling Using Dynamic Frequency Clocking”, Proc. IEEE Computer Society Annual Symposium on VLSI (ISVLSI) , 65-70, April 2002.
  31. A. Murugavel and N. Ranganathan, ”A Real Delay Switching Activity Simulator based on Petri net Modeling”, Proc. of Intl. Conf. on VLSI Design/ASP-DAC, 181-186, 2002.
  32. S. Bhanja and N. Ranganathan, ”Estimation of Switching Activity of Large Circuits Using Multiple Bayesian Networks”, Proc. of Intl. Conf. on VLSI Design/ASP-DAC, 187-192, 2002.
  33. S. Bhanja and N. Ranganathan, ”Dependency Preserving Switching Activity Estimation Using Bayesian Networks”, Proc. 38th IEEE/ACM Design Automation Conference (DAC), 209-214, June 2001.
  34. A. Murugavel, N. Ranganathan, R. Chandramouli and S. Chavali, ”Average Power in Digital CMOS Circuits Using Least Square Estimation”, Proc. of Intl. Conf. on VLSI Design, 215-220, Jan 2001.
  35. A. Ejnioui and N. Ranganathan,”Routing on Switch Matrix Multi-FPGA Systems”, Proc. of Intl. Conf. on VLSI Design, Jan 2000.
  36. A. Ejnioui and N. Ranganathan, ”Design Partitioning on single chip emulation systems”, Proc. of Intl. Conf. on VLSI Design, Jan 2000.
  37. V. Krishna, N. Ranganathan and S. Srinivasan, ”CREAM: Combined Register and Module Assigment with Floorplanning for Low Power Datapath Synthesis”, Proc. of Intl. Conf. on VLSI Design, Jan 2000 (nominated for Best Paper Award since ranked within top 5 papers out of 210 submissions).
  38. Hitoshi Oi and N. Ranganathan, ”A Cache Coherence Protocol for the Bidirectional Ring Based Multiprocessor”, Proceedings of Eleventh IASTED International Conference on Parallel and Distributed Computing and Systems (PDCS’99), 893-898, Cambridge, MA, November, 1999.
  39. H. Oi and N. Ranganathan, ”Utilization of Cache Area in On-Chip Multiprocessor”, Proc. International Symposium on High Performance Computing (ISHPC’99), Pp. 373-380, Kyoto, Japan, May 26-28, 1999.
  40. R. Chandramouli, N. Ranganathan,”Sequential Detection under Markov Dependence,” to appear in Proc. the 33rd Annual Conference on Information Sciences and Systems, The Johns Hopkins University, Baltimore, Maryland, March 17-19, 1999.
  41. R. Chandramouli and N. Ranganathan, ”Asymptotic Analysis of a Sequential Detector for Markov-Dependent Observations”, IEEE Signal Processing Workshop on Higher Order Statistics, Israel, June 1999.
  42. N. Vijaykrishnan and N. Ranganathan, ”Tuning branch predictors to support Java method invocation”, Proc. of 5th USENIX Conference on Object-Oriented Technologies and Systems (COOTS), San Diego, California, May 3-7 1999.
  43. V.N. Ramaswamy, K.R. Namuduri and N. Ranganathan, ”Context Based Lossless Intraframe Coding of Video Sequence Using Embedded Zerotree Wavelets”, Proc. of IEEE Intl. Symposium on Circuits and Systems, ISCAS99, Orlando, FL, May 30 - Jun 2, 1999.
  44. V.N. Ramaswamy, K.R. Namuduri and N. Ranganathan, ”Context Modeling of Wavelet Coefficients in EZW-Based Lossless Image Coding”, Proc. of IEEE Intl. Conf. on Acoustics, Speech and Signal Processing, ICASSP99, Phoenix, AZ, Mar 15-19, 1999.
  45. R. Venkataramana and N. Ranganathan, ”A Learning Automaton Based Framework for Task Partitioning and Scheduling with Multiple Costs in Heterogenous Computing Systems”, Proc. 1999 Heterogenous Computing Workshop, HCW99.
  46. A. Ejnioui and N. Ranganathan, ”Multi-Terminal Net Routing for Partial Crossbar-Based Multi-FPGA Systems”, Proc. ACM/SIGDA Seventh International Symposium on Field Programmable Gate Arrays, FPGA99, Feb 21-23, Monterey, CA, Pp. 176-185, 1999.
  47. R. Venkataramana and N. Ranganathan, ”A Learning Automaton Based Framework for Task Partitioning and Scheduling in Heterogenous Computing Systems”, Proc. 1999 ACM Symposium on Applied Computing, ACM SAC’99, San Antonio, TX, Feb 28 - Mar 2, Pp. 541-547, 1999.
  48. V. Krishna and N. Ranganathan and N. Vijaykrishnan,”Energy Efficient Datapath Synthesis Using Dynamic Frequency Clocking and Multiple Voltages”, Proc. of Intl. Conf. on VLSI Design, Goa, India, Jan 1999, Pp. 440-445.
  49. N. Vijaykrishnan and N. Ranganathan, ”Object Addressing Support for a Java Processor”, Proc. Sixth Intl. Conf. on Advanced Computing, Pp. 61-67, Dec 1998.
  50. V. Krishna, N. Ranganathan and N. Vijaykrishnan, ’An Energy Efficient Scheduling Scheme for Signal Processing Applications’, Thirty Second Asilomar Conference on Signals, Systems and Computers, November 1998, pp. 1057-1061.
  51. R. Venkatramana and N. Ranganathan, ”A Simple Adaptive Wormhole Routing Algorithm for MIMD Systems” Proc. of ICCD, October 1998. 1998.
  52. H. Oi and N. Ranganathan, ”A Comparative Study of Bidirectional Ring and Crossbar Interconnection Networks”, Proc. of Intl. Conf. on Parallel and Distributed Processing Techniques and Applications PDTA’98, Las Vegas, Nevada, July 13-16, 1998, Pp 883-890.
  53. R. Chandramouli, N. Vijaykrishnan and N. Ranganathan, ”SPRT for Weibull Distributed Integrated Circuit Failures”, Proc. SPIE Symposium on Microelectronic Manufacturing Yield, Reliability, and Failure Analysis IV, California, USA, Sept. 1998
  54. R. Chandramouli, N. Ranganathan and S. Kumar, ”Rate Control for a Video Coder Using Learning Automata”, to appear in Proc. IEEE International Conf. on SMC, San Diego, CA, Oct 11-14, 1998.
  55. R. Chandramouli, S. Kumar and N. Ranganathan, ”Joint Optimization of Quantization and On-line Channel Estimation for Low Bit-rate Video Transmission”, to appear in Proc. of Intl. Conf. on Image Processing ICIP, Oct 1998.
  56. R. Chandramouli and N. Ranganathan, ”Achieving Optimal Detection Through Discrete Diffusion Equations”, to appear in the Proceedings of the 9th IEEE Signal Processing Workshop on Statistical Signal and Array Processing, Portland, Oregon, Sept 14-16, 1998.
  57. G. Chiruvolu, R. Sankar and N. Ranganathan, ”An Adaptive Scheme for Better Utilization with QoS Constraints for VBR Video Traffic in ATM Networks”, Proc. of IEEE Symposium on Computers and Communications, ISCC ’98.
  58. R. Chandramouli and N. Ranganathan, ”On the Detection of a Constant Signal using Correlated Random Walk”, to appear in Proc. of IEEE Digital Signal Processing Workshop, Utah, August 1998.
  59. N. Vijaykrishnan, N. Ranganathan and R. Gadekarla, ”Object-Oriented Architectural Support for a Java Processor”, Proc. of 12th European Conf. on Object-Oriented Programming, ECOOP98, July 1998; Lecture Notes in Computer Science, Springer-Verlag Series, Edited by E. Jul, Springer-Verlag LNCS:1445.
  60. R. Chandramouli and N. Ranganathan, ”Quantization for Robust Sequential M-ary Signal Detection”, to appear in Proc. of Intl. Symposium on Circuits and Systems (ISCAS), 1998.
  61. R. Chandramouli, N. Ranganathan and S. Ramadoss, ”Error Resilient Coding for JPEG Image Transmission overWireless Fading Channels”, to appear in Proc. of Intl. Symposium on Circuits and Systems (ISCAS), 1998.
  62. P. Singh, W. Moreno, N. Ranganathan and H. Neinhaus, ”A VLSI Architecture for MPEG Audio Layer III Using Mixed Radix FHT”, to appear in Proc. of Intl. Symposium on Circuits and Systems (ISCAS), 1998 (invited paper).
  63. G. Chiruvolu, T. Das, R. Sankar and N. Ranganathan, ”Markov-chain based Scenic Model for VBR Video Traffic”, to appear in Proc. of IEEE Intl. Conf. on Communications (ICC’98), 1998.
  64. V. Krishna and N. Ranganathan, ”A New Approach to Power Management Methodology in CMOS Circuits”, Proc. of Great Lakes Symposium on VLSI, GLS98, New Orleans, 1998.
  65. R. Chandramouli and N. Ranganathan, ”Empirical Channel Matched Quantizer Design and UEP for Robust Image Transmission, Proc. of IEEE Data Compression Conference, Utah, March 1998.
  66. N. Ranganathan, R. Anand and G. Chiruvolu, ”A VLSI ATMSwitch Architecture for VBR Video Traffic”, Proc. of Intl. Conf. on VLSI Design, Jan 4-7, 1998; nominated for Best Paper Award consideration based on being ranked in the top 10 papers out of 200 submissions.
  67. V. Krishna, R. Chandramouli and N. Ranganathan, ”Computation of Lower and Upper Bounds for Switching Activity in CMOS Circuits”, Proc. of Intl. Conf. on VLSI Design, Jan 4-7, 1998.
  68. A. Rasquinha and N. Ranganathan, ”C3L: A Connected Component Labeling Chip”, Proc. of Intl. Conf. on VLSI Design, Jan 4-7, 1997.
  69. H. Oi and N. Ranganathan, ”Effect of Message Length and Processor Speed on the Performance of the Bidirectional Ring Multiprocessor”, Proc. of Intl. Conf. on Computer Design, ICCD, Austin, Texas, Oct 1997, Pp. 267-272.
  70. V.N. Ramaswamy, K.R. Namuduri and N. Ranganathan, ”Performance Analysis of Wavelet Filters for Lossless ZTW Encoding of Images”, Proc. Intl. Conf. on Image Processing, 1997.
  71. H. Oi and N. Ranganathan, ”Performance Analysis of the Bidirectional Ring Based Multiprocessor”, Proc. of ISCA 10th Intl. Conf. of Parallel and Distributed Computing Systems, PDCS ’97, New Orleans, LA, October 1997, Pp. 397-400.
  72. N. Ranganathan and R. Motamarri, ”A VLSI Architecture for Optimal Correspondence of String Subsequences”, to appear in Proc. of Intl. Workshop on Computer Architectures for Machine Perception, CAMP’97.
  73. N. Vijaykrishnan and N. Ranganathan, ”SUBGEN: A Genetic Approach to Subcircuit Extraction”, Proc. of Intl. Conf. on VLSI Design, Bangalore, Jan 1996.
  74. V. Krishna, N. Ranganathan and A. Ejnioui, ”A Tree Matching Chip”, Proc. of Intl. Conf. on VLSI Design, Bangalore, January 1996.
  75. N. Vijaykrishnan, R. Chandramouli and N. Ranganathan, ”Functional Reconfiguration for Fault-Tolerance: A New Approach”, Proc. IASTED Intl. Conf. on Modeling, Simulation and Optimization, Gold Coast, Australia, May 6-9, 1996.
  76. M. Patel and N. Ranganathan, ”PANTHER: A Parallel Neuro Systolic Architecture for Real Time Processing”, Proc. Intl. Conference on Neural Networks (ICNN), Washington D.C., June 3-6, 1996.
  77. V.N. Ramaswamy, K.R. Namuduri and N. Ranganathan, ”Lossless Image Coding Using Wavelets and Variable Block Size Segmentation”, Proc. of Intl. Symposium on Time-Frequency and Time-Scale Analysis, June 18-21, 1996, Paris, France.
  78. M. Patel and N. Ranganathan, ”A VLSI System Architecture for Intelligent Decision Making”, Proc. of Intl. Conf. on Application Specific Array Processors, Chicago, 1996.
  79. N. Ranganathan, S. Aruru and K.R. Namuduri, ”A VLSI System Architecture for Lossless Image Compression”, Proc. of Intl. Conf. on Pattern Recognition, ICPR, Aug 25-30, 1996.
  80. K.R. Namuduri, N. Ranganathan and H. Rashedi, ”SVBS: A High Resolution Medical Image Compression Scheme Using Slicing with Variable Block Size Segmentation” Proc. of Intl. Conf. on Pattern Recognition, ICPR 96, Aug 25-30, 1996.
  81. S. Arumugavelu and N. Ranganathan, ”SIMD Algorithms for Single Link and Complete Link Pattern Clustering”, Proc. of Intl. Conf. on Pattern Recognition, Aug 25-30, 1996.
  82. V.N. Ramaswamy, K.R. Namuduri and N. Ranganathan, ”Lossless Image Compression Using Wavelet Decomposition”, Proc. Intl. Conf. on Pattern Recognition, Aug 25-30, 1996.
  83. N. Ranganathan, N. Vijaykrishnan and N. Bhavanishankar, ”A Dynamic Frequency Linear Array Processor for Image Processing”, Proc. of ICPR-96, Aug 25-30, 1996.
  84. N. Ranganathan, S. Aruru and K.R. Namuduri,”A VLSI Chip for Image Compression Using Variable Block Size Segmentation”, Proc. of Intl. Conf. on Computer Design, ICCD 96, Austin, Oct 1996.
  85. N. Ranganathan, N. Vijaykrishnan and N. Bhavanishankar, ”A VLSI Array Architecture with Dynamic Frequency Clocking”, Proc. Intl. Conf. on Computer Design, Austin, Oct 1996.
  86. N. Saxena, S. Sarkar and N. Ranganathan, ”Mapping and Implementation of Baysian Belief Networks on Hypercube”, Proc. of Intl. Sym. on Parallel and Distributed Processing, SPDP’96, New Orleans, Oct 1996.
  87. M. Patel and N. Ranganathan, ”A VLSI System for Urban Traffic Control Applications”, Proc. of Intl. Sym. on Parallel & Distributed Processing, SPDP, New Orleans, Oct 1996.
  88. N. Ranganathan and R. Chandra, ”A Systolic Algorithm and Architecture for Convex Bipartite Matching”, Proc. of Intl. Conf. on High Performance Computing, HiPC’96, Trivandrum, Dec 18-22 1996.
  89. M. Kovac and N. Ranganathan, ”JAGUAR: A VLSI Architecture for Implementing JPEG Image Compression Standard”, Proc. of Intl. Conf. on VLSI Design, New Delhi, Jan 1995, ** Best Paper Award Winner.
  90. R. Sastry and N. Ranganathan, ”A VLSI Architecture for Approximate Tree Matching,” Proc. of Intl. Workshop on Parallel Processing, Bangalore, Dec 1994.
  91. R. Sastry and N. Ranganathan, ”A VLSI Architecture for Computing the Tree-to-Tree Distance,” Proc. Intl. Symp. on High Perf. Comp. Arch.,” Raleigh, NC, Jan 22-25, 1995.
  92. M. Kovac and N. Ranganathan, ”A Prototype VLSI chip for JPEG Image Compression Standard,” Proc. IEEE EDAC-EUROASIC-95 Conference, Paris, Mar 6-9, 1995.
  93. K.B. Doreswamy and N. Ranganathan, ”A Systolic Algorithm and Architecture for Image Thinning”, Proc. of Great Lakes Symposium on VLSI, March 1995.
  94. N. Ranganathan, ”Application Specific Parallel Architectures: Issues and Challenges”, Invited Position Paper for Workshop on Challenges in Parallel Processing, Intl. Conf. on Parallel Processing, Aug 1995.
  95. K.B. Doreswamy and N. Ranganathan, ”A VLSI Chip for Computing the Medial Axis Transform of Images”, Proc. of Computer Architectures for Machine Perception, CAMP 1995, Coma, Italy, Sept 1995.
  96. A. Ejnioui and N. Ranganathan, ”Systolic Algorithms for Tree Pattern Matching”, Proc. of IEEE Intl. Conf. on Computer Design, ICCD’95, Austin, Oct 1-3, 1995.
  97. A. Karimpuzha and N. Ranganathan, ”A Systolic Algorithm and Architecture for Computing B-Splines and Bezier Curves”, Proc. of Intl. Conf. on High Performance Computing, ICHPC, New Delhi, Dec 1995.
  98. M. Kovac and N. Ranganathan, ”ACE: A VLSI Chip for Galois Field Based Exponentiation, ”Proc. of Intl. Conf. on VLSI Design, Calcutta, India, Jan 5-8, 1994.
  99. A. Karimpuzha and N. Ranganathan, ”A Systolic Algorithm and Architecture for Computing B-Splines and Bezier Curves”, Proc. of Second Intl. Conf. on High Performance Computing, ICHPC, New Delhi, Dec 1995.
  100. M. Kovac and N. Ranganathan, ”ACE: A VLSI Chip for Galois Field Based Exponentiation,” Proc. of Intl. Conference on VLSI Design, Calcutta, India, Jan 5-8, 1994.
    101.
  101. N. Ranganathan, B. Parthasarathy and K. Hughes, ”A Parallel Algorithm and Architecture for Robot Path Planning,” Proc. of Intl. Parallel Processing Symposium, Cancun, Mexico, April 1994 .
  102. N. Ranganathan and S. Venugopal, ”An Efficient VLSI Architecture for Image Template Matching,” Proc. of International Conference on Parallel Processing, August 1994.
  103. N. Ranganathan and S. Venugopal, ”A VLSI Chip for Template Matching,” Proc. of Intl. Conf. on Computer Design, ICCD ’94, Boston, MA, October 1994.
  104. N. Ranganathan, K.R. Namuduri and S. Romaniuk, ”A Lossless Image Compression Algorithm Using Variable Block Size Segmentation,” Proc. of Intl. Conf. on Pattern Recognition, Jerusalem, October 1994.
  105. N. Ranganathan and S. Venugopal, ”A VLSI Architecture for Template Matching Based on Moment Preserving Pattern Matching,” Proc. of Intl. Conf. on Pattern Recognition, Jerusalem, October 1994.
  106. N. Ranganathan, R. Sastry, R. Venkatesan, J. Yoder and D. Keezer, ”SMAC: A Scene Matching Chip,” Proc. IEEE Intl. Conference on Computer Design ICCD93 , Cambridge, Massachusetts, October 1993.
  107. R. Sastry and N. Ranganathan, ”A VLSI Systolic Array for Approximate String Matching”, Proc. IEEE Intl. Conference on Computer Design, ICCD93, Cambridge, MA, October 1993.
  108. S. Kumar, N. Ranganathan and D. Goldgof, ”Parallel Algorithms for Circle Detection on a Mesh- Connected Array of Processors,” Proc. 8th Scandinavian Conf. on Image Analysis,” Tromso, Norway, May 1993.
  109. K. Hughes and N. Ranganathan, ”A Model for Determining Sensor Confidence”, Proc. IEEE Intl. Conference on Robotics and Automation, Atlanta, May 1993.
  110. R. Sastry, N. Ranganathan, R.C. Jain, ”VLSI Architectures for Depth Estimation using Intensity Gradient Analysis,” Proc. of Intl. Parallel Processing Symposium, Newport Beach, California, April 13-16, 1993.
  111. M. Kovac and N. Ranganathan, ”Systolic VLSI Implementations of Galois Field Arithmetic Algorithms,” Proc. IEEE EDAC-EUROASIC-93 Conference, Paris, February 22-25, 1993.
  112. R. Sastry, N. Ranganathan and H. Bunke, ”Hardware Algorithms for Polygon Matching,” Sixth International Conference on VLSI Design, Bombay, India, Jan 4-8, 1993.
  113. M. Kovac, N. Ranganathan and M. Varanasi, ”SIGMA: A VLSI Chip for Galois Field Based Multiplication and Division,” Proc. Sixth Intl. Conf. on VLSI Design, Bombay, Jan 4-8, 1993.
  114. R. Sastry, N. Ranganathan and H. Bunke, ”Systolic Architectures for Partial Polygon Recognition,” Proc. IAPR Workshop on Structural and Syntactic Pattern Recognition, Bern, Switzerland, August 1992.
  115. K. Hughes, A. Tokuta and N. Ranganathan, ”TRULLA : An Algorithm for Path Planning Among Weighted Regions by Localized Propagations,” Proc. Fifth Intl. Conference on Intelligent Robots and Systems, Iros’, Raleigh, North Carolina, July 7-10, 1992.
  116. A. Mukherjee, J. Flieder and N. Ranganathan, ”MARVLE: A VLSI Chip for Variable Length Encoding and Decoding,” Proc. IEEE Intl. Conference on Comuter Design ICCD , Cambridge, Massachusetts, October 11-14, 1992.
  117. M. Patel, P. McCabe and N. Ranganathan, ”SIBA: A VLSI Chip for Image Processing,” Proc. of International Conference on Pattern Recognition, The Hague, The Netherlands, August 1992, Vol. IV, pp. 15-18.
  118. V.K. Sundaresan, S. Nichani, N. Ranganathan and R. Sankar, ”A VLSI Hardware Accelerator for Dynamic Time Warping,” Proc. of International Conference on Pattern Recognition, The Hague, The Netherlands, August 1992, Vol. IV, pp. 27-30.
  119. R. Venkatesan, R. Sastry and N. Ranganathan, ”A VLSI Architecture for Hierarchical SceneMatching,” Proc. of International Conference on Pattern Recognition, The Hague, The Netherlands, August 1992, Vol. IV, pp. 214-217.
  120. K. Namuduri, R. Mehrotra and N. Ranganathan, ”Edge Detection using Gabor Filters,” Proc. of International Conference on Pattern Recognition, The Hague, The Netherlands, August 1992, Vol. III, pp.729-733.
  121. N. Ranganathan and K. R. Balaji, ”A VLSI Chip for Attribute-based Relational Databases,” Proc. International Conference on Information Systems and Management of Data, CISMOD, Bangalore, India, July 21-23, 1992, pp. 77-92.
  122. M. Kovac, N. Ranganathan and M. Varanasi, ”A Systolic Algorithm and Architecture for Galois Field Arithmetic,” Proc. of Intl. Parallel Processing Symposium, Beverly Hills, California, March 23-25, 1992, pp. 283-288.
  123. N. Ranganathan, S. Kurji and R. Mehrotra, ” A CMOS VLSI Chip for Motion Detection,” Proc. of Intl. Conference on VLSI Design, Bangalore, India, Jan 1992, pp. 209-214.
  124. N. Ranganathan, Patrick McCabe and M. Patel, ”A Programmable 2-dimensional Systolic Processor using 4-bit Processing Elements for Image Processing,” Proc. of Intl. Conference on VLSI Design, Bangalore, India, Jan 1992, pp. 215-220.
  125. S. Nichani and N. Ranganathan, ”Design of a High Speed VLSI Chip for Scale Space Computation,” Proc. of SPIE Conference on Applications of Artificial Intelligence X : Machine Vision and Robotics, Orlando, April 20-24, 1992.
  126. N. Ranganathan, R. Mehrotra and S. Subramaniam, ”A High Speed Systolic Architecture for Labeling Connected Components in an Image,”Proc. IEEE International Symposium on Parallel and Distributed Processing, Dallas, Texas, December 1-5, 1991, pp. 818-825.
  127. K. Chaudhury, R. Mehrotra and N. Ranganathan, ”A Parallel Algorithm for 3-D Point Pattern Matching,” Proc. IEEE Intl. Conference on Systems, Man and Cybernetics, Charlottesville, Virginia, Oct.13-16, 1991, pp. 105-111.
  128. N. Ranganathan and S. Henriques, ”A Systolic Architecture for LZ-based Decompression,” Proc. of Data Compression Conference, Snowbird, Utah, April 8-11, 1991, pp. 450-451.
  129. N. Ranganathan and S. Henriques, ”A Systolic VLSI Chip for Data Compression,” Proc. IEEE International Symposium on VLSI Design, New Delhi, Jan 4-8, 1991, pp. 310-311.
  130. N. Ranganathan, K. Namuduri and R.Mehrotra, ”An Architecture to Implement Multiresolution,” Proc. of IEEE Intl. Conf. on ASSP, Toronto, Canada, May 14-17, 1991.
  131. S. Henriques and N. Ranganathan, ”A Parallel Architecture for LZ-based Data Compression,” Proc. IEEE Intl. Symposium on Parallel and Distributed Processing, Dallas, Dec 9-13, 1990, pp. 262-266.
  132. S. Nichani and N. Ranganathan, ”SAP: Design of a Systolic Array Processor for Computations in Vision,” Proc. IEEE International Conference on Computer Design, ICCD ’90 , Cambridge, MA, September 17-19, 1990, pp. 315-318.
  133. K. Namuduri, R. Mehrotra and N. Ranganathan, ”Fast Spatiotemporal Filters,” Proc. 10th Intl. Conference on Pattern Recognition, Atlantic City, June 16-21, 1990, pp. 479-483.
  134. N. Ranganathan and R. Mehrotra, ”A VLSI Architecture for Dynamic Scene Analysis,” Proc. 10th Intl. Conf.on Pattern Recognition, Atlantic City, June 16-21, 1990, pp. 506-508.
  135. N. Ranganathan and H. N. Srinidhi, ”Effect of Data Compression Hardware on the Performance of a Relational Database Machine,” Proc. IEEE Intl. Conf. on Parallel Architectures & Databases (PARBASE ’90), Miami, March 7-9, 1990, pp.144-146.
  136. N. Ranganathan, S. Nichani and R. Mehrotra, ”A VLSI Architecture for Corner Detection,” Proc. Intl. Work. on Algorithms & Parallel VLSI Architectures, France, June 10-16, 1990.
  137. N. Ranganathan, S. Subramanian and R. Mehrotra, ”A High Speed VLSI Architecture for Connected Component Labeling,” Proc. Intl. Workshop on Algorithms and Parallel VLSI Architectures, France, June 10-16, 1990.
  138. N. Ranganathan and R. Mehrotra, ”A VLSI Based System for Motion Analysis in Scene Images,” Proc. IEEE Intl. Conf. on Tools for AI, Fairfax, VA, Oct 23-25, 1989, 592-597.
  139. A. Mukherjee, N. Ranganathan and M. Bassiouni, ”Adaptive and Pipelined VLSI Designs for Treebased Codes,” Proc. IEEE Intl. Conf. on Computer Design ( ICCD ’89), Cambridge, Massachusetts, Oct. 2-4, 1989, pp. 369-373.
  140. A. Mukherjee, N. Ranganathan and M. Bassiouni, ”On Software and Hardware Techniques of Data Encoding,” Proc. of Fifth Intl. Conf. on Data Engineering, Los Angeles, Feb. 6-10, 1989, pp. 208-215.
  141. N. Ranganathan and M. Shah, ”A Scale Space Chip,” Proceedings of 9th International Conference on Pattern Recognition, Roma, Italy, Nov. 14-18, 1988, pp. 420-424.
  142. A. Mukherjee, N. Ranganathan and M. Bassiouni, ”High Speed VLSI Encoding Chips for Supercomputers,” Proc. of 3rd Intl. Conf. on Supercomputing, Boston, May 15-20, 1988.
  143. A. Mukherjee, M. Bassiouni and N. Ranganathan, ”Improving Bandwidth of Communication Controllers,” Proc. of IEEE Intl. Conf. on Communications (ICC 88), Philadelphia, June 12-15, 1988.
  144. M. Bassiouni, N. Ranganathan and A.Mukherjee, ”Software and Hardware Enhancement of Arithmetic Coding,” Proc. of 4th Int. Conf. on SSDBM, Roma, Italy, June 21-23, 1988.
  145. M. Bassiouni, N. Ranganathan and A. Mukherjee, ”A Scheme for Data Compression in Supercomputers,” Proc. of Supercomputing 88, Orlando, Nov. 14-18, 1988, 272-278.


VLSI CHIPS DESIGNED/SUPERVISED

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  1. Design of a CMOS VLSI Chip for Invisible Digital Image Watermarking, 2003.
  2. Design of a CMOS VLSI Chip for Visible Digital Image Watermarking, 2003.
  3. Design of a CMOS VLSI Chip for Object Recognition in Images, 2002.
  4. Design of a CMOS VLSI Chip for Motion Estimation from Video, 1998.
  5. Design of a CMOS VLSI ATM Switch Prototype, 1997.
  6. Design of a CMOS VLSI Chip for Tree Matching, 1996.
  7. Design of a CMOS Chip for Connected Component Labeling, 1996.
  8. Design of a CMOS Chip for Cancer Detection using Digital Mamograms, 1996.
  9. Design of a CMOS VLSI Chip for Image Thinning, 1995.
  10. Design of a CMOS VLSI Chip for Tree Pattern Matching, 1995.
  11. Design of a CMOS VLSI Chip for Intelligent Decision Making, 1995.
  12. Design of a CMOS linear Array Processor with Variable Rate Clocking, 1995.
  13. Design of a CMOS VLSI Chip for Maximal Matching in Bipartite Graphs, 1995.
  14. Design of a Chip for Image Compression with Variable Size Segmentation, 1995.
  15. Design of a Chip for Contiguous Binary String Matching CBS Problem, 1995.
  16. Design of a CMOS VLSI Chip for Approximate Tree Matching, 1994.
  17. Design of a CMOS VLSI Chip for Template Matching, 1994.
  18. Design of a CMOS VLSI Chip for JPEG Image Compression Standard, 1994.
  19. Design of a CMOS VLSI Chip for Approximate String Matching, 1993.
  20. Design of a CMOS VLSI Chip for Polygon Recognition, 1993.
  21. Design of a CMOS VLSI Chip for Hierarchical Scene Matching, 1992.
  22. Design of a Systolic CMOS Chip for Join Computation in RDBMS Systems, 1991.
  23. Design of a Systolic Array Processor CMOS Chip for Dynamic Scene Analysis, 1991.
  24. Design of a 2-D Systolic Array processor CMOS Chip for Image Processing, 1991.
  25. Design of a Memory-based CMOS VLSI Chip for JPEG Baseline Compression, 1991.
  26. Design of a Systolic Array CMOS Chip for LZ-based Data Compression, 1990.
  27. Design of a Run-length Based Compression CMOS Chip, 1990.
  28. Design of SIGMA: Systolic Chip for Galois Field-based Multiply/Divide, 1990.
  29. Design of a Prototype CMOS Chip for Huffman-based Decompression, 1990.
  30. Design of a Systolic Array Processor Chip for Scale Space Computation, 1989.
  31. Design of a Prototype CMOS Chip for Huffman-based Data Compression, 1987.
  32. Design of an nMOS chip for Polygonal Mask Generation, 1985.
  33. Design of an nMOS Pipeline Wallace Multiplier Chip, 1984.
INVITED TALKS

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  1. Power Estimation and Optimization, Distinguished Speaker Lecture Series, Cadence Inc., Boston, September 2002.
  2. VLSI Systems for Data Compression, SVCE College of Eng., Uni. of Madras, May 1998.
  3. Application Specific VLSI Systems, Uni. of Texas at El Paso, Feb 1998.
  4. Image Transmission over Wireless Channels, UCF, Orlando, IEEE DVP Speaker, Nov 1997.
  5. Lossless Data Compression, ITEM University, Cuernavaca, October 1997.
  6. VLSI For Pattern Matching, UCF, Orlando, April 1997.
  7. Application Specific VLSI Systems, Uni. of Houston, April 1997.
  8. Data Compression, IIT, Bombay, IEEE DVP Speaker, Dec 1995.
  9. Data Compression, East Tenn. State Uni. ACM chapter, Johnson City, TN, Nov 1993.
  10. ”VLSI Hardware for Data Compression,” ACM/IEEE Tampa Bay Section, Nov 18, 1992.
  11. ”VLSI for Data Compression,” University of Central Florida CS Colloquium, Sept. 23, 1992.
  12. ”Performance in Very Large Databases”, K.J. Somaiya Institute, Bombay, Jan 1992.
  13. ”VLSI Algorithms and Architectures”, IIT-Madras and IEEE Madras Section, Dec 1990.
  14. ”VLSI Design”, Regional Engineering College, University of Madras, July 1989.
  15. ”Data Compression Hardware”, IEEE and ACM Tampa Bay Section, October 1988.
  16. ”Higher Education in Engineering”, St. Peter’s High School, Tanjore, June 1988.
  17. ”Data Compression”, Indian Institute of Technology, Madras, India, June 1988.
  18. ”Graduate Education in U.S. Universities”, Regional Engineering College, Tiruchi, July 1985.