Computer
Logic Design Lab (CDA3201L)
Spring 2004
Lab Exercise 5
Pre Lab: Consider the second half of this Logic Works tutorial: http://www.itee.uq.edu.au/~cse/LogicWorks_Tutorial/
Consider the Basic Function Generator, Basic Oscilloscope, and Circuit Connection Devices (X10 probe) tutorials: Introduction to the First Year Lab
Consider this guide to the oscilloscope model that is most common in our lab: Oscilloscope Guide and for more in depth information: XYZ’s of Oscilloscopes
Note: Use LEDs and resistors to display the Q
outputs in each step. Use pull-up resistors as required for inputs. Include
step 4 Logic Works timing diagram in your report.
1. Design and verify the operation of an S’ R’ latch (used as a debounced switch) using 7400 NAND logic gates and an input SPDT switch as follows:
Logic Works: Ground the single (common) terminal of a SPDT switch and use the other 2 terminals as inputs to the latch (upper terminal = S’). Normal position is down (latch is reset).
Breadboard: Ground the 2 upper left pins of a blue dip switch with 4 switches (provided for you) and use the 2 upper right pins as inputs to the latch (upper terminal = S’). This design yields a SPDT switch. Normal position is left (latch is reset).
2. Verify the operation in Logic Works and on the Breadboard of a 7476 JK flip-flop using SPST switches as inputs to the J, K, preset’, and clear’ inputs. Use the Q output of the debounced switch in step 1 above as the clock input (move the switch to S’ position and then back to R’ position to generate a clock pulse).
3. Verify the operation in Logic Works and on the Breadboard of a 7474 D flip-flop using SPST switches as inputs to the D, preset’, and clear’ inputs (you should use the same preset’ and clear’ switches as in 2 above, with J now labeled as D). Use the Q output of the debounced switch in step 1 above as the clock input (move the switch to S’ position and then back to R’ position to generate a clock pulse). The 7474 outputs are updated with the rising edge of the clock pulse.
4. Repeat step 2 above in Logic Works using the Logic Works clock instead of the debounced switch as the 7476 clock input. Use single step operation to generate a timing diagram for all possible combinations of J and K inputs, and for preset and clear operations.
5. Repeat step 2 above on the Breadboard using the function generator TTL output as the 7476 clock input, and simultaneously observe this signal and the 7476 Q output on the oscilloscope, with J, K, preset’, and clear’ inputs set to logic 1. Describe or illustrate the waveforms in your report. The lab instructor will assist you with this setup.
6. In Logic Works, design and verify the operation of an S R latch using Nor gates (generic or 7402) and SPST switches. Display the Q and Q’ outputs.
7. In Logic Works, design and verify the operation of a gated S R latch using Nand gates (generic or 7400) and SPST switches. Display the Q and Q’ outputs.
8. In Logic Works, design and verify the operation of a clocked T flip-flop using a D flip-flop (generic or 7474), logic gate(s), and SPST switches. Hint: Only 1 generic gate is required.
Q & A
1. Briefly explain switch bounce and how the switch debounce circuit in
step 1 works.
2. Explain why the SR latch should not have an input combination of S=1
and R=1.
IMPORTANT: Bring your Bread board implementation and Logic Works circuit file
to the lab. Lab grade will depend on the working of the circuit and will be
checked off by the lab instructor.