SELECTED PUBLICATIONS ON VEDIC MATHEMATICS:

1. Himanshu Thapliyal and M.B  Srinivas, "High Speed Efficient N X N Bit Parallel Hierarchical Overlay Multiplier Architecture Based On Ancient Indian Vedic Mathematics", Enformatika (Transactions on Engineering, Computing and Technology),Volume 2,Dec 2004, pp.225-228.
2. Himanshu Thapliyal and M.B Srinivas ,”An Efficient Method of Elliptic Curve Encryption Using Ancient Indian Vedic Mathematics", Proceedings of the 48th IEEE MIDWEST Symposium on Circuits and Systems (MWSCAS 2005), Cincinnati, Ohio, USA, August 7-10, 2005, pp. 826-829. IEEE Press.
3. Himanshu Thapliyal and  M.B Srinivas ,”Design and Analysis  of  A Novel Parallel Square and Cube  Architecture Based On Ancient  Indian  Vedic Mathematics", Proceedings of the 48th IEEE MIDWEST Symposium on Circuits and Systems (MWSCAS 2005), Cincinnati, Ohio, USA, August 7-10, 2005, pp.1462-1465. IEEE Press.
4. Himanshu Thapliyal and M.B Srinivas, “VLSI Implementation of  RSA Encryption System using  Ancient Indian Vedic Mathematics ”, Proceedings of SPIE -- Volume 5837 VLSI Circuits and Systems II, Jose F. Lopez, Francisco V. Fernandez, Jose Maria Lopez-Villegas, Jose M. de la Rosa, Editors, June 2005, pp. 888-892
5. Himanshu Thapliyal and Hamid R. Arabania,"High Speed Efficient N Bit by N Bit Division Algorithm And Architecture Based On Ancient Indian Vedic Mathematics", Proceedings of VLSI04, Las Vegas, U.S.A, June 2004, pp. 413-419(CSREA Press).
6. Himanshu Thapliyal and Hamid R. Arabania, “A Novel Parallel Multiply and Accumulate (V-MAC) Architecture Based on Ancient Indian Vedic Mathematics”, Proceedings of VLSI04, Las Vegas , U.S.A, June 2004, pp. 440-446(CSREA Press).
7. Himanshu Thapliyal ,“Novel Design of NXN Bit Decomposed Multiplier Based on Ancient Vedic Mathematics”, Proceedings of the 3rd UK ACM SIGDA Workshop on Electronic Design Automation,  Southampton , U.K. , Sep 2003.