SELECTED PUBLICATIONS AND PREPRINTS:

  1. Himanshu Thapliyal and Nagarajan Ranganathan, "Testable Reversible Latches for Molecular QCA", Proceedings of the 8th International Conference on Nanotechnology (IEEE NANO 2008), Arlington, TX, Aug 2008. pp. 699-702 (Invited Presentation after peer review process).
  2. Himanshu Thapliyal, Hamid R. Arabnia and M.B Srinivas, "Efficient Reversible Logic Design of BCD Subtractors”,  Transactions on Computational Sciences Journal, Springer, Vol.3, LNCS 5300, pp.99-121, 2009.( in Press)
  3. Himanshu Thapliyal and A. P. Vinod, “Design of Reversible Sequential Elements With Feasibility of Transistor Implementation”, Proceedings of the 2007 IEEE International Symposium on Circuits and Systems(ISCAS 2007), New Orleans, USA, May 2007, pp. 625-628.
  4. Himanshu Thapliyal and A. P. Vinod, “Designing efficient online testable reversible adders with new reversible gate”, Proceedings of the 2007 IEEE International Symposium on Circuits and Systems(ISCAS 2007), New Orleans, USA, May 2007, pp.1085-1088.
  5. Himanshu Thapliyal, Hamid R. Arabnia, Rajnish Bajpai, Kamal K. Sharma, “Combined Integer and Variable Precision (CIVP) Floating Point Multiplication Architecture for FPGAs”, Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, PDPTA 2007,Las Vegas, June 2007, pp.449-450
  6. Himanshu Thapliyal, Hamid R. Arabnia and A.P.Vinod, "Combined integer and floating point multiplication architecture(CIFM) for FPGAs and its reversible logic implementation" ,  Proceedings of The 49th IEEE International Midwest Symposium on Circuits and Systems, Puerto Rico ,  August 2006, pp. 438-442  (Nominated for the Student Best Paper Award).
  7. Himanshu Thapliyal and Mark Zwolinski, "Reversible Logic to Cryptographic Hardware: A New Paradigm", Proceedings of The 49th IEEE International Midwest Symposium on Circuits and Systems, Puerto Rico , August 2006, pp. 342-346 (Nominated for the Student Best Paper Award ).
  8. Himanshu Thapliyal and M.B Srinivas, “The New BCD Subtractor and Its Reversible Logic Implementation", Lecture Notes in Computer Science, Published by Springer-Verlag Berlin/Heidelberg (ISSN: 0302-9743), Advances in Computer Systems Architecture, Edited by C. Jesshope and C. Egan: Proceedings of the Eleventh Asia-Pacific Computer Systems Architecture Conference - ACSAC 2006: (ISBN: 3-540-29643-3), vol. 4186/2006, pp. 469-475, Sep 2006
  9. Himanshu Thapliyal and M.B Srinivas, “Novel Reversible “TSG” Gate and Its Application for Designing Reversible Carry Look Ahead Adder and Other Adder Architectures”, Lecture Notes in Computer Science, Published by Springer-Verlag Berlin/Heidelberg (ISSN: 0302-9743), Advances in Computer Systems Architecture, Edited by T. Srikanthan, J. Xue and C. H. Chang: Proceedings of the Tenth Asia-Pacific Computer Systems Architecture Conference - ACSAC 2005: (ISBN: 3-540-29643-3), vol. 3740/2005, pp. 775-786, October 2005 .
  10. Himanshu Thapliyal and M.B Srinivas, “Design of Wallace tree multiplier and other components of a quantum ALU using reversible TSG gate”,  SPIE -- Volume 6264 Quantum Informatics 2005, Yuri I. Ozhigov, Editor, 62640H (May. 31, 2006) (11Pages).
  11. Himanshu Thapliyal and Sumedha K. Gupta, "Design of Novel Reversible Carry Look-Ahead BCD  Subtractor", Proceedings of 9th  IEEE Conference on Information Technology(ICIT),  India , 18th-21st December, 2006. pp.253-258. IEEE Computer Society Press.
  12. Himanshu Thapliyal, Saurabh Kotiyal and M.B Srinivas, “Novel BCD Adders and their Reversible Logic Implementation for IEEE 754r Format”, Proceedings of the 19th  IEEE/ACM International Conference on VLSI Design and 5th International Conference on Embedded Systems (VLSI Design 2006), Hyderabad, India, Jan 4-7, 2006,pp. 387-392. IEEE Computer Society Press
  13. Himanshu Thapliyal, Neela Gopi, Pavan Kumar and M.B Srinivas, “Low Power Hierarchical Multiplier and Carry Look-Ahead Architecture”,   Proceedings of the 4th ACS/IEEE International Conference on Computer Systems and Applications (AICCSA-06), Dubai , March 2006, pp. 88-92, IEEE Computer Society Press.
  14. Himanshu Thapliyal and  M.B Srinivas ,”Design and Analysis  of  A Novel Parallel Square and Cube  Architecture Based On Ancient  Indian  Vedic Mathematics", Proceedings of the 48th IEEE MIDWEST Symposium on Circuits and Systems (MWSCAS 2005), Cincinnati, Ohio, USA, August 7-10, 2005, pp.1462-1465. IEEE Press.
  15. Himanshu Thapliyal and M.B Srinivas, “VLSI Implementation of  RSA Encryption System using  Ancient Indian Vedic Mathematics ”, Proceedings of SPIE -- Volume 5837 VLSI Circuits and Systems II, Jose F. Lopez, Francisco V. Fernandez, Jose Maria Lopez-Villegas, Jose M. de la Rosa, Editors, June 2005, pp. 888-892
  16. Himanshu  Thapliyal, M. B. Srinivas and Mark Zwolinski, “A Beginning in the Reversible Logic Synthesis of Sequential Circuits,” in Proceedings of the Military and Aerospace Programmable Logic Devices (MAPLD) International Conference, 2005.
  17. Himanshu Thapliyal and M.B  Srinivas,  "High Speed Efficient N X N Bit Parallel Hierarchical Overlay Multiplier Architecture Based On Ancient Indian Vedic Mathematics",  Enformatika (Transactions on Engineering, Computing and Technology),Volume 2,Dec 2004, pp.225-228.