Download Latest Papers and Patent (2011-2008) !

1. H. Thapliyal and N. Ranganathan, “Design of Efficient Reversible Logic Based Binary and BCD Adder Circuits”, to appear ACM Journal of Emerging Technologies in Computing Systems, Sep 2012.
2. N. Ranganathan and H. Thapliyal , “Conservative Logic Element for Design of Quantum Dot Cellular Automata Circuits”, United States Patent 7880496, Feb 2011
3. H. Thapliyal and N. Ranganathan, “A new design of the reversible subtractor circuit”, Proceedings of the 11th IEEE International Conference on Nanotechnology (IEEE NANO), Portland, Oregon, August 2011, pp.1430-1435.
4. S. Kotiyal, H. Thapliyal, and N. Ranganathan, “Design of a reversible bidirectional barrel shifter”, Proceedings of the 11th IEEE International Conference on Nanotechnology (IEEE NANO), Portland, Oregon, August 2011, 463-468.
5. M. Nachtigal, H. Thapliyal, and N. Ranganathan, “Design of a reversible floating-point adder architecture”, Proceedings of the 11th IEEE International Conference on Nanotechnology (IEEE NANO), Portland, Oregon, August 2011, pp. 451-456.
6. H. Thapliyal and N. Ranganathan, “A New Reversible Design of BCD Adder", Proceedings of Design Automation and Test in Europe (DATE), Grenoble, France, March 2011, pp.1180-1183.
7. H. Thapliyal and N. Ranganathan, “Design of Reversible Sequential Circuits Optimizing Quantum Cost, Delay and Garbage Outputs", ACM Journal of Emerging Technologies in Computing Systems, Vol. 6, No. 4, Article 14, Dec 2010
8. H. Thapliyal, N. Ranganathan and R. Ferreira, “Design of a Comparator Tree Based on Reversible Logic", Proceedings of the 10th IEEE International Conference on Nanotechnology (IEEE NANO), Seoul, Korea, Aug 2010, pp. 1113-1116.
9. H. Thapliyal and N.Ranganathan, “Reversible Logic Based Concurrent Error Detection Methodology For Emerging Nanocircuits", Proceedings of the 10th IEEE International Conference on Nanotechnology (IEEE NANO),Seoul, Korea, Aug 2010, pp.217-222.
10. M. Nachtigal, H. Thapliyal and N. Ranganathan, "Design of a Reversible Single Precision Floating Point Multiplier Based on Operand Decomposition", Proceedings of the 10th IEEE International Conference on Nanotechnology (IEEE NANO), Seoul, Korea, Aug 2010,pp.233-237.
11. S. Kotiyal, H. Thapliyal and N. Ranganathan, “Design of A Ternary Barrel Shifter Using Multiple-Valued Reversible Logic", Proceedings of the 10th IEEE International Conference on Nanotechnology (IEEE NANO), Seoul, Korea, Aug 2010,pp.1104-1108.
12. H. Thapliyal and N. Ranganathan, “Reversible Logic Based Concurrently Testable Latches for Molecular QCA”, IEEE Transactions on Nanotechnology, vol. 9, No. 1, pp. 62-69, Jan 2010.
13. H. Thapliyal and N. Ranganathan, "Design of Reversible Latches Optimized for Quantum Cost,Delay and Garbage Outputs", Proceedings of the 23rd International Conference on VLSI Design (VLSI Design) , Bangalore, India, Jan 2010,pp.235-240 (Acceptance rate=21%)
14. H. Thapliyal and N. Ranganathan, ”Bit Conserving Logic as a Potential Integration Platform for Hybrid Molecular & Nanoscale CMOS-Based Architectures”, Proceedings of the 2009 Nanoelectronic Devices for Defense & Security (NANO-DDS) Conference, Fort Lauderdale, Sept 2009.
15. H. Thapliyal and N. Ranganathan, “Concurrently Testable FPGA Design for Molecular QCA Using Conservative Reversible Logic Gate”, Proceedings of the International Symposium on Circuits and Systems (ISCAS), Taipei, May 2009, pp. 1815 - 1818. (Acceptance rate = 45%)
16. H. Thapliyal and N. Ranganathan, “Design of Efficient Reversible Binary Subtractors Based on A New Reversible Gate ", Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI), Tampa, May 2009, pp.239-234.(Acceptance Rate=24%).
17. H. Thapliyal and N. Ranganathan, " Conservative QCA Gate (CQCA) for Designing Concurrently Testable Molecular QCA Circuits",  Proceedings of the 22nd International Conference on  VLSI Design (VLSI Design), Delhi, India, Jan 2009, pp.511-516. (Acceptance Rate: 18.43%, 59 regular papers from 320 submissions).
18. H. Thapliyal, H.R. Arabnia and M.B. Srinivas, “Efficient Reversible Logic Design of BCD Subtractors”, Springer Transactions on Computational Sciences Journal, Vol. 3, LNCS 5300, pp. 99-121, 2009.
19. H. Thapliyal and N. Ranganathan, "Testable Reversible Latches for Molecular QCA", Proceedings of the 8th International Conference on Nanotechnology (IEEE NANO), Arlington, TX, Aug 2008. pp. 699-702 (Invited Paper).

If you need any paper that is not listed here but listed in Google scholar, please drop me an email at h.t@duke.edu