The Energy Efficient Internet Project

Literature

This page contains an annotated literature review for the Green TCP/IP project. This literature review contains papers from conference, journals, and technical reports. Standards and specification documents can be found here. Our own publications can be found here. In cases where a paper can be found on the web (typically, on the paper author's web site), a link is given. However, it cannot be guaranteed that the link points to a version of the paper matching the citation.

NOTE: This page is not being updated at this time. The last update was on March 5, 2007.



This literature review is organized into the following sections:

Power consumption of the Internet, networks and networking equipment

To the best of our knowledge, Suresh Singh and his students are the only other group addressing the economic/environmental cost of power consumption of the Internet. A seminal paper from Gupta and Singh is:

TCP/IP and other protocols

Energy consumption of TCP/IP has been thoroughly studied in the context of wireless networks. In wireless networks turning on the transmitter is very expensive (in power consumption). Thus, many of the works on TCP/IP focus on methods of bunching packet transmissions.
  1. B. Wang and S. Singh, " Computational Energy Cost of TCP," Proceeding of INFOCOM, March 2004. The results from an energy measurement study of TCP are presented. It is shown that the kernel and copy from kernel to user space consume the majority of energy.

  2. H. Singh, and S. Singh, " Energy Consumption of TCP Reno, Newreno, and SACK in Multi-Hop Wireless Networks", Proceedings of the 2002 ACM SIGMETRICS international conference on measurement and modeling of computer systems, pp. 206 - 216, 2002. Compares energy consumption of TCP variants (Reno, Newreno, and SACK). SACK is found to be more efficient if the idle power consumption (of the device) is significant, while Newreno is found to be more efficient if idle power consumption is not significant.

  3. S. Agrawal, and S. Singh, " An Experimental Study of TCP’s Energy Consumption over a Wireless Link", Proceedings of the 4th European Personal Mobile Communications Conference, 2001. This paper examines how to reduce TCP power consumption while remaining within TCP standards. Experiments measuring power consumption are done with TCP's timestamp option, window scaling option, SACK option, header prediction, and MTU size. It is shown that MTU size has, by far, the largest effect. The paper reports a 25% reduction in power when large MTUs are used.

  4. R. Krashinsky, and H. Balakrishnan, " Minimizing Energy for Wireless Web Access with Bounded Slowdown", Proceedings of ACM Mobicom, pp. 119-130, 2002. This paper describes the Bounded-Slowdown (BSD) protocol for 802.11 that dynamically adapts to network activity. The goal is to keep RTTs to less than 100 milliseconds (the normal beacon time of non-BSD 802.11 in Power-Saving Mode (PSM), which is too coarse grained for TCP) to keep TCP performance up. BSD slowly decays the time between awake periods after a transmission. This exploits the burstiness of web traffic.

  5. G. Anastasi, M. Conti, E. Gregori, and A. Passarella, "A Power Saving Architecture for Web Access from Mobile Computers", Proceedings of the 2nd International IFIP Networking Conference (Networking 2002), Lecture Notes in Computer Science Vol. 2345, pp. 240-251, 2002. This work applies indirect TCP to a wireless network for power savings. A PS-TP (Power-Saving Transport Protocol) for single-hop wireless bridged to TCP/IP for a wired portion is developed and evaluated. PS-TP dynamically tunes power saving parameters to network traffic conditions by tuning time-outs and sleeping times. PS-TP appears to do data clumping to minimize the number of times a transmitter must be turned on.

  6. R. Min, and A. Chandrakasan, " Top Five Myths about the Energy Consumption of Wireless Communication", ACM SIGMOBILE Mobile Communication and Communications Review, Vol.6, No. 4, 2002. This paper is a summary of conclusions reached by the authors when researching wireless energy consumption. They conclude that energy efficient communication protocol layers must be based upon accurate models of the underlying hardware with any inaccuracies leading to expectations that vary widely from reality and that application specific design and energy-quality scalability can increase the energy efficiency of communication protocols significantly.

  7. C. Jones, K. Sivalingam, P. Agrawal, and J. Chen, " A Survey of Energy Efficient Network Protocols for Wireless Networks", Wireless Networks, Vol. 7 No. 4, pp. 343-358, July 2001. Energy efficiency is an important consideration in wireless networks as most devices are powered by batteries. This paper is a survey of energy efficient protocols and low power design in wireless networks.

  8. V. Tsaoussidis, and H. Badr, " TCP-Probing: Towards an Error Control Schema with Energy and Throughput Performance Gains", Proceedings of the 8th IEEE Conference on Network Protocols, 2000. Discusses the addition of a probing mechanism and an immediate recovery strategy to TCP to improve throughput while reducing energy expenditure.

  9. V. Tsaoussidis, H. Badr, X. Ge, and K. Pentikousis, " Energy/Throughput Tradeoffs of TCP Error Control Strategies", Proceedings of the 5th IEEE Symposium on Computers and Communications (ISCC 2000), 2000. Another paper examining TCP variants and their relative energy efficiencies in wireless/error-prone environments. The authors conclude that none of the variants [Tahoe, Reno and NewReno] show a clear cut advantage under all situations with Tahoe being the most energy efficient TCP variant overall.

  10. V. Tsaoussidis, H. Badr, and R. Verma, " Wave and Wait Protocol (WWP): Low Energy, High Throughput for Mobile IP-Devices", Proceedings of the 7th IEEE Conference on Network Protocols, 1999. This paper descibres a toy protocol to conserve energy at the expense of throughput. The protocol backs off more than usual whenever congestion becomes noticeable. Thus, retransmissions are reduced to keep energy consumption down.

Servers, server clusters and data centers

With the advent of data centers and large scale server hosting, large numbers of servers with high power requirements are concentrated in a small area creating "hot spots" of energy consumption. Within the last few years this has become an important research area with several active projects to reduce the energy consumption of servers and data centers.
  1. R. Sharma, C. Bash, C. Patel, R. Friedrich, and J. Chase, "Balance of Power: Dynamic Thermal Management for Internet Data Centers", Technical Report HPL-2003-5, Hewlett Packard, February 2003. Focuses on dynamic load balancing in data centers, where in order to maintain a uniform temperature and to avoid high temperature localities, the server load is dynamically allocated. The authors have also developed a simulation model of a typical server data center using computational fluid dynamics.

  2. P. Bohrer, E. Elnozahy, T. Keller, M. Kistler, C. Lefurgy, C. McDowell, and R. Rajamony, " The Case for Power Management in Web Servers", Power Aware Computing, Graybill and Melhem, editors, Kluwer Academic Publications, January 2002. The authors of this important work analyze the workload of web servers and identify that it is possible to reduce the power consumption during low utilization periods. They propose using dynamic voltage and frequency scaling to save energy under moderate loads.

  3. C. Lefurgy, K. Rajamani, F. Rawson, M. Kistler, and R. Keller, " Energy Management for Commercial Servers", IEEE Computer, Vol. 36, No. 12, pp. 39-48, December 2003. Commercial SMP servers are built to maximize performance and energy consumption is a secondary concern. This paper discusses several methods for reducing the energy consumption of servers.

  4. R. Bianchini, " Research Directions in Power and Energy Conservation for Clusters", Technical Report DCS-TR-466, Department of Computer Science, Rutgers University, November 2001. This report identifies several characteristics in server clusters that can be exploited for achieving power and energy savings and explores several methods that can be utilized. Methods mentioned include concentrating workload into a subset of available servers and functionality specialization.

  5. E. Pinheiro, R. Bianchini, E. Carrera, and T. Heath, " Load Balancing and Unbalancing for Power and Performance in Cluster-Based Systems", Proceedings of the Workshop on Compilers and Operating Systems for Low Power, 10th International Conference on Parallel Architectures and Compilation Techniques, September 2001. This paper focuses on power and energy conservation by dynamically turning on and turning off cluster nodes. The load on the cluster is concentrated on a number of nodes and redundant nodes are shut down. The authors have gained energy savings of over 30%.

  6. J. Chase, C. Anderson, P. Thakar, R. Doyle, and A. Vahdat, " Managing Energy and Server Resources in Hosting Centers", Proceedings of the 18th ACM Symposium on Operating System Principles, pp. 103-116, October 2001. Presents an architecture for managing server clusters with energy as the primary optimized resource. The number of active servers in the cluster is varied depending upon load.

  7. J. Chase, and R. Doyle, “ Balance of Power: Energy Management for Server Clusters", Proceedings of the 8th Workshop on Hot Topics in Operating Systems, May 2001. Proposes an energy conscious server switching scheme where servers within a cluster are activated and deactivated based upon the cluster load. As the utilization levels of the active servers increase beyond a preset threshold deactivated servers are reactivated.

  8. W. Felter, T. Keller, M. Kistler, C. Lefurgy, K. Rajamani, R. Rajamony, F. Lawson, B. Smith, and E. Van Hensbergen, " On the Performance and Use of Dense Servers", IBM Journal of Research and Development, Vol. 47, No. 5/6, p. 671, September/November 2003. This paper describes the development of a prototype densely packed server cluster that outperforms a traditional server with equivalent power consumption by a factor of two when running multiple independent workloads. Concludes that with present technology, traditional servers offer better performance at certain tasks and that installations can optimize performance/cost by running a mix of servers.

  9. S. Gurumurthi, A. Sivasubramanium, M. Kandemir, and H. Franke, " DRPM: Dynamic Speed Control for Power Management in Server Class Disks", Proceedings of the International Symposium on Computer Architecture, pp. 169-179, June 2003. This paper proposes reducing the power dissipation of server class disks and disk arrays by using dynamic rotations per minute (DRPM) disks that can vary the rotation speed in response to workload variations. Also discusses the engineering obstacles involved and methods of overcoming them.

  10. E. Carrera, E. Pinheiro, and R. Bianchini, " Conserving Disk Energy in Network Servers", Proceedings of the 17th International Conference on Supercomputing, pp. 86-97, June 2003. The authors analyze several methods of reducing the disk power consumption in network servers including shutting down disks during idle periods, replacing high performance disks with many low performance disks, combining high and low performance disks and multi-speed disks that vary rotational speed to lower power consumption. They conclude that multi-speed disks provide the best solution.

  11. M. Elnozahy, M. Kistler, and R. Rajamony, " Energy Conservation Policies for Web Servers", Proceedings of the 4th USENIX Symposium on Internet Technologies and Systems, March 2003. This paper analyzes the reduction in server power consumption when dynamic voltage scaling and request batching techniques are applied.

  12. K. Rajamani, and C. Lefurgy, " On Evaluating Request-Distribution Schemes for Saving Energy in Server Clusters ", Proceedings of IEEE International Symposium on Performance Analysis of Systems and Software , March 2003. This paper identifies key factors in server/cluster systems and server workloads that affect the energy efficiency of a server cluster and shows their effect on a power aware request distribution scheme.

  13. W. Feng, M. Warren, and E. Weigle, " The Bladed Beowulf: A Cost-Effective Alternative to Traditional Beowulfs", Proceedings of the IEEE International Conference on Cluster Computing, pp. 245-255, September 2002. Explores the use of Tranmeta Crusoe processors in Beowulf clusters instead of AMD or Intel processors in order to reduce thermal power dissipation and achieve to greater processor density. Also presents a new benchmark that considers performance with respect to power consumption.

  14. E. Elnozahy, M. Kistler, and R. Rajamony, " Energy Efficient Server Clusters", Proceedings of the Second Workshop on Power Aware Computing Systems, February 2002. Focuses on evaluating several policies for minimizing energy consumption in server clusters. The technologies used include dynamic processor voltage scaling and switching cluster nodes on/off in response to cluster workload. >From their results the authors conclude that a combination of coordinated voltage scaling of cluster nodes and switching nodes on/off provides the best savings.

  15. J. Mitchell-Jackson, " Energy Needs in an Internet Economy: A Closer Look at Data Centers", Master's Thesis, Energy and Resources Group, University of California at Berkeley, May 2001. Examines the energy consumption patterns of data centers and attempts to quantify future growth in energy consumption. Concludes that present data center power requirements are often overestimated.

Technical reports from Department of Energy and the Lawrence Berkeley National Laboratory

The Environmental Energy Technologies Division and Lawrence Berkeley National Laboratory has the mission, "to perform research and development leading to better energy technologies and reduction of adverse energy-related environmental impacts." This includes work in Internet and office equipment energy consumption.
  1. J. Roberson, C. Webber, M. McWhinney, R. Brown, M. Pinckard, and J. Busch, " After-hours Power Status of Office Equipment and Inventory of Miscellaneous Plug-Load Equipment”, Technical report LBNL-53729, Energy Analysis Department, Lawrence Berkeley National Laboratory, January 2004. This study has collected data on the extent to which electronic office equipment is either shutdown or in low power mode when not used. Shows that approximately 60% of computers are powered on when inactive.

  2. J. Koomey, C. Calwell, S. Laitner, J. Thornton, R. E. Brown, J. Eto, C. Webber, and C. Cullicott, " Sorry, Wrong Number: The Use and Misuse of Numerical Facts in Analysis and Media Reporting of Energy Issues.", Annual Review of Energy and the Environment 2002, Vol. 27, pp. 119-158, November 2002. the authors present four examples of the use of misleading or wrong numbers in the energy analysis field. They analyze the errors in these examples and describes methods for evaluating statistics.

  3. C. Webber, R. Brown, A. Mahajan, and J. Koomey, " Savings Estimates for the ENERGY STAR Voluntary Labeling Program: 2001", Status report LBNL-48496, Lawrence Berkeley National Laboratory, February 2002. This study estimates and forecasts the savings achieved and expected through that use of the ENERGY STAR labeling program. With 100% market penetration for office equipment, it is estimated that 33 Billion US$ will be saved in energy costs during the 2001-2010 period.

  4. C. Webber, J. Roberson, R. Brown, C. Payne, B. Nordman, and J. Koomey, " Field Surveys of Office Equipment Operation Patterns", Technical report LBNL-46930, Lawrence Berkeley National Laboratory, September 2001. Survey of 11 offices after working hours to determine turn-off rates for various types of office equipment. The results show that 54% of desktop computers were switched on, 44% was switched off and only 3% of desktop computers were placed in power saving mode at night.

  5. K. Kawamoto, J. Koomey, B. Nordman, R. Brown, M. Piette, M. Ting, and A. Meier, " Electricity Used by Office Equipment and Network Equipment in the U.S.: Detailed Report and Appendices”, Technical Report LBNL-45917, Energy Analysis Department, Lawrence Berkeley National Laboratory, February 2001. This technical report is a comprehensive study of the electricity consumption of office and network equipment. It concludes that the total energy consumption is approximately 74 TWh/year which is 2% of the total electricity consumed in the US. The power management enabled rate for desktop computers is only 25% and complete saturation of power management in office equipment would save 17TWh/year.

  6. R. Latta, " A Look at Residential Energy Consumption in 1997," DOE/EIA-0632(97), Energy Information Administration, Office of Energy Markets and End Use, US Department of Energy, November 1999. This is a detailed breakdown of US residential energy consumption in the year 1997. Shows that the average household consumption of electricity is 10,215 KWh per year.

Dynamic power management

In dynamic power management (DPM) subsystems are powered-down when not needed. This can be within a chip, within a "box", or the entire box itself. Key challenges to DPM are in predicting, detecting, and utilizing idle periods for power down.
  1. A. Papathanasiou, and M. Scott, "Energy Efficiency through Burstiness", Proceedings of the 5th IEEE Workshop on Mobile Computing Systems and Applications (WMCSA'03), pp. 44-53, October 2003.The authors propose redesigning operating systems to increase the burstiness of the workload of system devices in order to conserve energy. The proposed methods include pre-fetching and coordinating requests to devices among applications running in the system. By aggregating requests together, larger idle periods can be exposed.
  2. E.-Y. Chung, L. Benini, A. Bogliolo, Y.-H. Lu, and G. De Micheli, "Dynamic power management for nonstationary service requests", IEEE Transactions on Computers, Vol. 51, No. 11, pp. 1345-1361, November 2002. The Markov decison process based approaches to dynamic power management usually assume stationary workloads as the optimization problem is resolved off-line. By using a windowing method, this paper extends Markov decision process based methods to non-stationary workloads.

  3. W. Chedid, and C. Yu, " Survey on Power Management Techniques for Energy Efficient Computer Systems", Laboratory Report, Mobile Computing Research Lab, Cleveland State University, 2002. A survey of both static and dynamic power management tools for computer systems. The authors survey and summarize present energy conservation techniques for processors, computer systems and server clusters.

  4. T. Simunic, L. Benini, P. Glynn, and G. De Micheli, " Dynamic Power Management For Portable Systems" [PS], Proceedings of the Sizth International Conference on Mobile Computing and Networking [MOBICOM], pp. 11-19, August 2000. The authors present a model based upon time indexed semi-markov decision process to handle user request inter-arrival times in portable systems. The dynamic power management algorithm based upon this model is compared with other existing algorithms and shown to provide greater power savings when used in a laptop hard disk and WLAN card.

  5. Q. Qiu, Q. Wu, and M. Pedram, "Dynamic power management of complex systems using generalized stochastic petri nets", Proceedings of the 37th Design Automation Conference 2000, pp. 352-356, June 2000. The authors use perti nets to model the behaviour of compex systems as they contend that using Markov models can be too difficult. The petri net models are then converted to continuous time Markov decision processes and the optimization policy is generated. The poposed technique shows an improvement of 20% over previous techniques.

  6. Y. Hsiang, E. Chung, T. Simunic, L. Benini, and G. De Micheli, " Quantitative Comparison of Power Management Algorithms", Proceedings of the conference on Design, Automation and Test in Europe, pp. 20-26, 2000. Dynamic Power Management (DPM) shuts down devices during idle periods. Thus, we have idle periods (where no requests arrive) and working periods (where requests can be served). This paper proposes and evaluates several algorithms for DPM of a disk in a WindowsNT laptop.

  7. L. Benini, A. Bogliolo, and G. De Micheli, " A Survey of Design Techniques for System Level Dynamic Power Management", IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 8, No. 3, pp. 231-248, 2000. Survey of system-level dynamic power management techniques. Analyzes and discusses techniques that use dynamic reconfiguration to reduce power consumption.

  8. E.-Y. Chung, L. Benini, and G. De Micheli, "Dynamic power management using adaptive learning tree", Digest of Technical Papers, 1999 IEEE/ACM International Conference on Computer-Aided Design, pp. 274-279, November 1999. Uses learning tree algorithms. As correct or incorrect predictions are made, the predictions and the corrections are stored in a tree based data structure and used to make the next prediction.

  9. L. Benini, A. Bogliolo, G. A. Paleologo, and G. De Micheli, "Policy optimization for dynamic power management" IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems,Vol. 18, No. 6, pp. 813-833, June 1999. This paper presents the dynamic power management problem as finite-state model based upon Markov decision processes. Power vs. performance is resolved using stochastic policy optimization.

  10. Q. Qiu, and M. Pedram, "Dynamic power management based on continuous-time Markov decision processes", Proceedings of the 36th Design Automation Conference, pp. 555-561,June 1999. Introduces continuous time Markov decision process based policy optimization models. Claimed to provide a more accurate representation of the actual device.

  11. Y. Lu, T. Simunic, and G. De Micheli, " Software Controlled Power Management", Proceedings of the Seventh International Workshop on Hardware/Software Codesign, pp. 157-161, 1999. Develops and evaluates disk spin-down algorithms within the scope of ACPI and WindowsNT. Contains good tutorial on ACPI and DPM. DPM algorithms can be classed as predictive and stochastic. The paper shows that an adaptive algorithm can beat “time-out after idleness” for power savings due to the bursty nature of disk accesses.

  12. L. Benini, A. Bogliolo, and G. De Micheli, " Dynamic Power Management of Electronic Systems", Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design, pp. 696-702, 1998. Survey of system-level dynamic power management techniques. Analyzes and discusses idleness detection and shutdown, system design and modeling and optimization.

  13. C.-H. Hwang, and A. C.-H. Wu, "A predictive system shutdown method for energy saving of event-driven computation", Digest of Technical Papers, 1997 IEEE/ACM International Conference on Computer-Aided Design, pp. 28-32, November 1997. Uses exponential smoothing to predict the duration of the next idle time. Compared with Srivastava, et al, this method does not need offline analysis and can adopt to system behaviour changes.

  14. M. B. Srivastava,A. P. Chandrakasan, and R. W. Brodersen, " Predictive system shutdown and other architectural techniques for energy efficient programmable computation", IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 4, No. 1, pp. 42-55, March 1996. First major paper to consider using predictive methods for controlling dynamic power management. Uses offline analysis to derive an model of the application's on-off behavior and uses this model to calculate the duration of the next off time. Prediction does not change with system behaviour change.

Software and operating system optimizations

Programming optimizations and operating system scheduling have been investigated for a power consumption perspective. Some of the key works are listed below.
  1. C. Krintz, Y. Wen, and R. Wolski, " Predicting Program Power Consumption", UCSB Technical Report #2002-20. Analyzes the degree to which power dissipation caused by program execution can be measured. The authors propose a method where the power consumption of the entire device is considered and show that for certain classes of instructions, the power consumption can be closely modeled.

  2. M. Lee, M. Fujita, V. Tiwari, and S. Malik, " Power analysis and minimization techniques for embedded DSP software", IEEE Transactions on VLSI Systems, Vol. 5, No. 1, pp. 123-125, 1997. Develops an instruction-level power analysis model based on physical current measurements for an embedded DSP core. Using this model, the authors propose an instruction scheduling approach to minimize energy consumption that achieves savings of 11% to 56% on a set of programs.

  3. J. Lorch, and A. Smith, " Software Strategies for Portable Computer Energy Management", IEEE Personal Communications Magazine, Vol. 5, No. 3, pp. 60-73, June 1998. Many hardware components have low and high power consumption modes. By using software to select the optimum mode to suit requirements, the power consumption of devices can be reduced. The authors present a survey of solutions to software energy management issues.

  4. J. Russell, and M. Jacome, " Software Power Estimation and Optimization for High Performance, 32-bit Embedded Processors", Proceedings of the International Conference on Computer Design, pp. 328-333, 1998. Determined that there is no statistical significance in the variation of power consumption of different instructions for the i960 RISC processor. Thus, minimizing execution time means also minimizing energy consumption - use a good optimizing compiler. For a DSP (other papers cited), instruction reordering, instruction packing, operand reordering, register allocation, and memory assignment can result in power savings.

  5. V. Tiwari, S. Malik, and A. Wolfe, " Power Analysis of Embedded Software: A First Step Towards Software Power Minimization", IEEE Transactions on VLSI Systems, Vol. 2, No. 4, pp. 437-445, 1994. This paper proposes a power analysis technique to model the power cost of the software component of an embedded system. The authors develop an instruction level power consumption model of the processor which is then used to estimate the energy consumption of a given program.

  6. V. Tiwari and T. C. Lee, " Power Analysis of a 32-bit Embedded Microcontroller", VLSI Design Journal, Vol. 7, No. 3, 1998. The authors measure the power consumption of a commercial 32-bit RISC embedded microcontroller at the processor instruction level and develop an energy consumption model for the processor. They conclude that shutting down unused CPU modules dynamically can save power, but to maximize the savings, interactions between modules when executing instructions also has to be considered.

  7. V. Tiwari, S. Malik, and A. Wolfe, " Compilation techniques for low energy: An overview", Proceedings of the 1994 Symposium on Low Power Electronics, 1994. Discusses possible techniques for reducing the energy consumption of programs by compiler-level optimizations. They include using energy efficient instruction sequences and reducing the number of memory operands. The authors achieve a maximum of 40% low energy consumption.

Wireless and adhoc sensor networks

The nodes in ad hoc sensor networks are powered by batteries that are difficult or impossible to replace. Therefore, energy consumption is a major design constraint. Many research efforts are underway to reduce the energy consumption of sensor and other mobile devices and thus increase their operating lifetime.
  1. E. Shih, P. Bahl, and M. Sinclair, " Wake on Wireless: An Event Driven Energy Saving Strategy for Battery Operated Devices", Proceedings of the Eighth Annual ACM Conference on Mobile Computing and Networking, pp. 160-171, September 2002. This paper proposes a method of increasing the battery lifetime of 802.11 wireless devices by adding a separate very low power receiver that listens for a "wakeup" signal on a separate frequency when the device is in a low-power state. Receipt of such signal would trigger a wake up of the device. The high power, high bandwidth receiver does not have to be powered on continuously. The authors have built a working prototype that shows significant gains in device lifetime.

  2. C. Guo, L. Zhong, and J. Rabaey, " Low Power Distributed MAC for Ad Hoc Sensor Radio Networks", Proceedings of Global Telecommunications Conference (GLOBECOM) 2001, Vol. 5, pp. 2944-2948, November 2001. This paper proposes several desirable design requirements for low power sensor networks. And the authors describe a radio system where a very low power receiver is used to listen on a signal channel for a "wakeup beacon" indicating incoming data for that node while the relatively high power receiver/transmitter is powered down.

Proxy services for resource limited devices

Proxying is a means to enhance the capabilities of a resource limited device or to enhance the performance of a system. A proxying device "answers for" other devices.

Processor architecture optimizations

Significant work has been done in reducing processor energy consumption. There are two motivations for this work. One motivation is to reduce heat (and thus allow even more transistors and function to be placed in a processor chip). Another motivation is to increase batter life for laptop and mobile computers.
  1. L. Benini and G. Micheli, " System-Level Power Optimization: Techniques and Tools", ACM Transactions on Design Automation of Electronic Systems, Vol. 5, No. 2, pp. 115-192, 2000. This is a short tutorial on power-conscious system level design. The described methods are: 1) memory optimization techniques to exploit cache usage, 2) hardware-software partitioning starting to optimally split tasks between h/w and s/w, 3) Instruction level optimization to select a minimum-power instruction mix for commodity processor, 4) control-Data-flow transformations, 5) variable-voltage techniques (cited as probably the most effective way to reduce power consumption), 6) dynamic-power management for putting subsystems or systems into standby when inactive, and 7) Interface power minimization to minimize off-chip communications.

  2. J. Chang, and M. Pedram, " Energy Minimization Using Multiple Supply Voltages", IEEE Transactions on VLSI Systems, Vol. 5, No. 4, pp. 436-443, 1997. Presents a dynamic programming technique to minimize average energy consumption by using different supply voltage levels per operation.

  3. A. Chandrakasan, M. Potkonjak, R. Mehra, J. Rabaey, and R. W. Brodersen, " Optimizing power using transformations", IEEE Transactions on Computer Aided Design, Vol. 14, No. 1, pp. 12-51, 1995. Presents a high-level synthesis system for minimizing power consumption in CMOS circuits using architectural and computational transformations.

  4. K. Choi, and A. Chatterjee, "Efficient Instruction-Level Optimization Methodology for Low-Power Embedded Systems", Proceedings of the 14th International symposium on Systems synthesis, pp. 147-152, 2001. This paper presents several algorithms to solve instruction scheduling and reordering problems in low power embedded systems. Includes experimental results to corroborate predictions.

  5. Dynamic Clock Scaling - Project at the Department of Computer Science, University of Colorado, Boulder. Energy is proportional to clock frequency and proportional to the square of operating voltage. Voltage and frequency are a sliding scale. This paper proposes to scale clock speed as needed by a task (e.g., a user interface task need not run faster than human perception, a deadline driven task need not finish before the deadline). The main question addressed in this paper is if past process performance can be used to determone future CPU frequency.

  6. J. Henkel, " A Low Power Hardware/Software Partitioning Approach for Core-based Embedded Systems", Proceedings of the 36th ACM/IEEE conference on Design automation, pp. 122-127, 1999. This paper discusses hardware/software partitioning to reduce power in embedded systems. The author proposes clustering instructions for a particular module/core in the processor together and reducing power to unneeded modules. With the addition of extra logic circuits, it is shown that significant energy savings can be obtained.

  7. C. Hsieh, L. Chen, and M. Pedram, " Microprocessor Power Analysis by Labeled Simulation", Proceedings of the Design Automation and Test in Europe 2001, pp. 182-189, 2001. Discusses instruction-level power microanalysis to use the micro-architectural details of a CPU to provide the power consumption for each active instruction in each cycle.

  8. B. Klass, D. Thomas, H. Schmit, and D. Nagle, " Modeling Inter-Instruction Energy Effects in a Digital Signal Processor", Power-Driven Microarchitecture Workshop, ISCA, 1998. The authors describe a technique for modeling instruction level power consumption that takes into account inter-instruction power consumption by introducing an "overhead cost". The accuracy of the model is within 8% of the actual value.

  9. S. Lee, "Instruction-level Power Modeling of Acoustic Beamforming in Distributed DSP Systems", Presentation for HCS Research Lab, University of Florida. This presentation covers instruction-level power estimation for a sonar beamforming application in an embedded system with a DSP. An instruction-level power table is built for the ADSP-2116M processor. Small variance was found for instructions. Energy optimization is accomplished by parallelizing tasks.

  10. S. Manne, A. Klauser, and D. Grunwald, “ Pipeline Gating: Speculation Control for Energy Reduction”, Proceedings of 25th International Symposium on Computer Architecture, pp. 132-141, 1998. Uses a form of speculation control to reduce the amount of unnecessary work and therefore reduce energy consumption in super-scalar processors.

  11. J.-M. Masgonty, C. Arm, S. Durand, M. Stegers, T. Schneider, and C. Piguet, " Low-Power Design of an Embedded Microprocessor Core", Proceedings of the 22nd European Solid-State Circuits Conference, 1996. Surveys the various techniques to reduce power in embedded processors. Includes several areas (although not in any depth) that are not covered in some of the other papers we have on embedded processors including gated clock techniques, and hierarchical memories.

  12. T. Mudge, " Power: A First-Class Architectural Design Constraint", IEEE Computer, Vol. 34, No. 4, pp. 52-58, 2001. A high-level overview paper of architectural consideration for reducing power consumption. For server farms, power consumption accounts for 25% of the facility cost. Reducing voltage and reducing activity are key to reducing power consumption. Techniques discussed are: clock gating, half-swing/half-frequency clocks, asynchronous logic, memory systems, buses, and operating system (finish no task before its deadline). Sidebar on Intel XScale core that uses a PLL with a fast resynch to be able to switch frequencies in less than 20 microseconds.

  13. P. Petrov and A. Orailoglu, " Performance and Power Effectiveness in Embedded Processors - Customizable Partitioned Caches", IEEE Transactions on Computer-Aided Design, Vol. 20, No. 11, pp. 1309-1318, 2001. This paper descibes application-specific customization technique for the data cache to reduce power consumption in embedded processors.

  14. J. Pouwelse, K. Langendoen, and H. Sips, " Dynamic Voltage Scaling on a Low-Power Microprocessor", Proceedings of the 7th international conference on Mobile computing and networking, pp. 251-259, 2001. This paper describes voltage scaling on microprocessors to conserve power.

  15. R. San Martin and J. Knight, " Power-Profiler: Optimizing ASICs Power Consumption at the Behavioral Level," Proceedings of the 32nd ACM/IEEE conference on Design automation conference, pp. 42-47, 1995. This paper describes ASIC power reduction strategies through behavioral synthesis.

  16. R. Sasanka, C. Hughes, and S. Adve, " Joint Local and Global Hardware Adaptations for Energy", Proceedings of 10th International Conference on Architectural Support for Programming Languages and Operating systems, pp.144-155, 2002. This paper proposes algorithms to minimize energy consumption in hardware when running multimedia applications.

  17. P. Stanley-Marbell, M. Hsiao, and U. Kremer, " A Hardware Architecture for Dynamic Performance and Energy Adaptation", Springer Verlag Lecture Notes in Computer Science, vol. 2325, pp. 33-52, 2003. This paper develops a Power Adaptation Unit (PAU) for detecting regions of runtime application execution where there is a possibility to run a device at a decreased power level with voltage/frequency scaling and not compromise performance. In particular, imbalances in memory and CPU activity are detected/predicted by the PAU and the CPU turned-off during memory activity. Pipeline stalls are used to detect when a CPU can be turned-off.

  18. J. Villarreal, D. Suresh, G. Stitt, F. Vahid, and W. Najjar, " Improving Software Performance with Configurable Logic", Kluwer Journal on Design Automation of Embedded Systems, Vol. 7, No. 4, pp. 325-339, 2002. This paper examines supplementing microprocessors with reconfigurable logic and adding reconfigurable logic to speed-up the processes as well as reduce energy consumption.

  19. V. Zyuban, " Unified Architecture Level Energy-Efficiency Metric", Proceedings of the 12th ACM Great Lakes Symposium on VLSI, pp. 24-29, 2002. This paper describes design modifications for energy efficiency in microprocessors and develops a new metric for evaluating ISA features.

Human factors and power management

Human factors can play a role in determining when power management can be enabled and also in evaluating the user impact of power management. A simple and elegant idea is presented by Dalton and Ellis.

Miscellaneous

Some miscellaneous papers are:
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Last updated on March 5, 2007