Satish Pulikala Bhat

3715, Quixote Blvd.,                                                                                                               Phone No.: 813-866-8384

Tampa, FL - 33613                                                                                                              Email: psatishbhat@yahoo.com

Objective:

To seek challenging a full time position so as to apply my skills in Computer Engineering and to contribute positively in the growth of the organization

Academic Qualification:

M.S. in Computer Engineering (August 2002), University of South Florida, Tampa. Present G.P.A. is 3.50

B.E. in Electronics & Communication (October 1998), R.V. College of Engineering, India with 66.29%

Computer Skills:

CAD Tools: Cadence (Verilog XL and HSPICE simulations)

Languages: C, C++ (Certified by CMC Ltd., A government of India Enterprise)

Database: Oracle 8.0, MS Access (Certified by CMC Ltd., A government of India Enterprise)

Operating Systems: Windows 9x/2000, UNIX, DOS, Windows NT

Assembly Languages: Intel 8085/6

Work Experience:

University of South Florida, Tampa, Florida

May 2001 - Present, Graduate Assistant, Physical Plant

• Maintain the University Green-lights program and Building Audit database

September 2000 - Present, Research Assistant, Department of Computer Science & Engineering

• Review technical papers in the area of Combinatorial Auctions
• Debug codes written in C++
• Create web pages in HTML

Aptech Computers Ltd., India

April 1999 - July 2000, Project Manager/Software Engineer

• Designed databases for small retail outlets
• Developed applications on Oracle 7.x and Developer 2000

Projects Implemented in C++/C:

• Computation of Minimum area packing represented by an arbitrary sequence-pair
• Fiduccia-Mattheyses bi-partitioning heuristic for edge-weighted hyper-graphs
• PODEM (Path- Oriented Decision Making) algorithm, a test-generating algorithm for combinational logic circuits
• Data Traffic Analysis in LAN/ WAN with respect to different application layer protocols.

Projects Implemented using CADENCE:

• Designed and implemented 8-Bit Full Adder, 8-Bit 4-Input Multiplexer, 4 X 4 Binary Multiplier, Binary Counters, Universal Shift Registers, using Cadence tools and Spice Verification and Simulation packages. Designed individual gates and basic modules, using P and N MOS transistors
• Designed an 8-bit register file having eight 8-bit registers
• Designed a Micro-controller circuit for Newspaper Vending Machine using random logic
• Designed and implemented hardware for Bubble Sort algorithm using all components designed throughout the course-work
• Designed and implemented a Low Power UART

Papers:

A Survey of Gate Level Power Optimization Techniques, University of South Florida, April 2001